EDMA on OMAP-L138

Hi Mukul,

Thank You for replying.

The EDMA TRM claims that, for SAM in constant addressing mode, source address to be aligned to a 256-bit aligned address (5 LSBs of address must be zero)

I understand that EMIF doesn't support constant addressing mode hence the above statement is not applicable.

Just to have confirmation that to have SAM in constant addressing mode I have to make the Least 5-Significant bits to zero correct? Just confused with (LSB I guess it should be LSb)

I am not sure whether this community is right place or not to ask the following question.

In that case can we have the following address schema between EMIFA and External UART Controller?

[A5:A0] are left unconnected to the external UART controller, so that when the UARTs tx or rx address is configured in increment mode it doesn't address any other internal register.

[A8:A6] will be used to address the External UART internal registers.

[A12:A9] and one of the EMIF's chip select will be used as chip select to the External UART Controller.

Regards,

GSR

Mukul,

Here the requirement is that there is a external peripheral such as a FPGA/CPLD or a EMIFA based Ethernet/UART controller chipsets.

The FPGA will have a memory mapped register at a constant address and we need to perform EDMA transfer from System Memory [DDR] to the EMIFA Constant Address. So we need to know if the OMAPL1x supports constant mode DMA when the source or destination is a constant address within the EMIFA Bus.

In our design, we are using a CPLD which acts as an interface to external world analog signals coming into the OMAPL1x. We need to know if we can perform a EDMA transfer between the DDR and the CPLD using Constant Addressing mode.

Thanks,

Ravindra

Hi Mukul,

Just one clarification. Even though EMIFA supports Increment Mode only can we have the following configuration, so that the EDMA reads always from one constant address.

For example if we have a 1-Byte location which acts as a constant address in a peripheral which is connected over EMIFA and the FIFO size for that perpheral is around 64 Bytes.

We are performing a read transaction from the peripheral.

Then A_CNT = 1, B_CNT = 64, C_CNT = 1, SRC_DST_BIDX  = (1 << 16), and SRC_DST_CIDX = 0.

So that the source address is not incremented and the Destination address such as SDRAM location is incremented by 1-Byte.

Can you please clarify this.

Thank You & Regards,

GSR

Hi

Yes you can use INCR mode, with src/dst index set to 9 , to serve a fixed address. This would be very similar to what you would've done for EDMA based transfers to serial ports (UARTs, McASP) with FIFO.

A good description on how to use INCR mode instead of constant/FIFO mode with EMIFA is an errata of another device (has a similar EMIFA and EDMA3 IP)

http://focus.ti.com/lit/er/sprz234n/sprz234n.pdf

(Pg 9, 2.1.4).

Hope this helps.

Regards

Mukul

Hi Ravindra

My previous post in response to GSR's query applies to your forum post also. The errata link should help you comprehend how to do transfers to FIFOs / fixed addresses over EMIFA using EDMA3 INCR mode.

Regards

Mukul

Hi Mukul,

Thank You for replying.

Regards,

GSR