CCS/TMS320C6748: nand flash can not boot up after power-on again

Have you tried to test the binary on the core TI eval board from which the flash and boot schematic was reused. I would try to ensure that the boot image is working on the TI eval platform to ensure that the boot image is correctly created.

Whether there is a mismatch between AISGen and GEL is hard to say as you have not indicated how the PLL and module clocks are setup in your AIS configuration. When the boot fails, can you please run the debug GEL file as indicated in the application notes here:

https://www.ti.com/lit/an/spracm8/spracm8.pdf

Debug GEL file: 7573.OMAPL1x_debug.gel

Please provide the log from the debug Gel file so we can understand the setup. 

Other questions:

1. Did you erase the NAND before programming it ?

2. Other than 8bit and 16 bit bus width, are there any differences in ECC requirements and the size of page, spare area, etc ?

3. Is the application running from device internal memory or external DDR memory. GEL and AISGen config for this should be compared as well. For sanity check, make sure you can open memory browser in CCS after AISGen file boot is attempted and see if you can read and write to DDR regions.

Hope this helps.

Regards,

Rahul 

user6345424 said:

When I change block 0 to block 1 in line 279, which is in nandwriter.c in the nandwriter project, the board can be started after burning to nand flash.

I previously downloaded OMAP-L138_FlashAndBootUtils_2_36 from TI’s official website. I changed block 0 to block 1 of line 279 in nandwriter.c in the nandwriter project , compile and generate a new nandwriter.out file, re-burn the program, and the board can be started. Before the modification, the program was burned into block 0 of nand flash, and after modification, it was burned into block 1.

What I want to ask is, why the 16-bit nand flash on the TMS320C6748 board must be burned into block 1 to start it?

Please check Appendix A Boot mode selection (Foot note 3) in the bootloader application notes :

https://www.ti.com/lit/an/spraat2f/spraat2f.pdf . 

For NAND boot mode BOOT[6:5] determines which NAND block is used by the ROM as the first block for booting. For BOOT[6:5] = 00, NAND boot begins in block 1 and does not apply any initial PLL configuration before the first block read.

user6345424 said:

And I  have a new problem now :
We have made more than a dozen sets of boards based on the C6748 core board. Other boards can now be burned to nand flash and started successfully, but one board even fails to debug. The error reported  as follows:

Is it possible that the nand flash burned?  I tested the voltage of the board with a multimeter, and the voltage was normal. How to solve this problem?  

This issue is most likely an hardware issue but it could also be due to marginal issues with your DDR SDRAM timing settings. the address 0xC0000000 corresponds to DDR initialization. Please note that when you have an AISGen file used for booting the device, you should not use a GEL file as the AISGen and ROM on the device will configure the clocks. From your CCS log it appears that you are connecting with a GEL file.

GEL file is used only in debug mode when ROM has not performed any initialization and you need an script over the emulator to setup the clocks, PSC and DDR on the platform. When you connect to the core, please check the Program counter to identify if the core is still in the L2 ROM  or if it has exited into your application when the device is in that state.

Regards,

Rahul