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MSGQ in DSP/BIOS LINK

Other Parts Discussed in Thread: OMAP3530, DM3725

Hi everyone,

I want to use MSGQ in DSP/BIOS LINK to implement the inter-processor communication in DM3725/OMAP3530.

Now I wonder how many MSQ can be queued in MSGQ?
MSGQ in DSP/BIOS LINK will use ZCPY protocol, related ZCPY components will use IPS, IPS will use IPC module in DM3725/OMAP3530.
Since the FIFP depth of mailbox in IPC is four words, does that mean the number of MSG in MSGQ will be limited to 4?
If not, how many MSG can be queued in MSGQ?

Your helps will be benefical!

Thank you!

  • Armstrong Xu said:

    Now I wonder how many MSQ can be queued in MSGQ?
    MSGQ in DSP/BIOS LINK will use ZCPY protocol, related ZCPY components will use IPS, IPS will use IPC module in DM3725/OMAP3530.
    Since the FIFP depth of mailbox in IPC is four words, does that mean the number of MSG in MSGQ will be limited to 4?
    If not, how many MSG can be queued in MSGQ?

     

    Armstrong Xu,

    There is no limitation on the number of messages that can be queued in the MSGQ. The MSQ depth is not dependent on the hardware mail box depth. New messages can be allocated (unless the memory gets exhausted) and queued, which can be accessed by the reader asynchronously.

    Regards,

    Nag

    (If your question is answered, please click the  Verify Answer  button below)

  • Hi Nagbhushan,

      For example

     If ARM has already sended 4 MSGs to MSGQ of DSP,and to notify the DSP, the IPS component in DSP/BIOS LINK has sended 4 messages to IPC mailbox, but DSP does not read the MSGs and messages from IPC mailbox and MSGQ in time.

    When ARM send the 5th MSG to MSGQ, what will happen? The 4th message in IPC mailbox will be overwritten? DSP will not process the 5th MSG in MSGQ for there is only 4 notice? Or something else? Or it is the user's responsibility to handle this problem.

    Thanks,

    Xu

  • Xu,

    Here is how the messaging works using the MSGQ module:

    The reader creates the queue. When the writer allocates the message and calls the put() API to send the message to the reader, the message pointer is immediately sent to the reader queue. All new messages put by the writer will be transferred to the reader queue in the same way. The queuing does not happen in the mail box and happens in the reader queue. So the number of messages is not limited to the mailbox depth. The messages from the queue will be removed when ever the reader reads the messages.

    Please go through the following webex presentations to understand the MSGQ functionality and features:

    http://processors.wiki.ti.com/index.php/DSPBIOS_LINK_WebEx_Presentations

    For presentation specific to Message Queue

    http://ti.webex.com/webex/playback.php?FileName=http://learningmedia.ti.com/public/2008_DSP_BIOS_LINK1.50/DSP_BIOS_LINK1.50_Overview_trng_part2.wrf

    Regards,

    Nag

  • Hi Nag,

    Thanks for your help.

    I am not familiar with DSP/BIOS LINK, and I don't know when DSP  sends the message to the reader, how it l informs ARM that "you got a message in your que"?

    In OMAP3530 MSGQ sample, it seems like that MSGQ in DSP side use ZCPY MQT. When DSP call the put() API, I think it wil call ZCPYMQT_send ().

    In ZCPYMQT_send,  besides the QUE_put() which will queue the message header in reader que, there is also a IPS_notify which will notify the ARM, see the code below.

        QUE_put ((QUE_Handle) &(ctrlPtr->fmDspList), bufPtr) ;
        HAL_cacheWbInv ((Ptr) bufPtr, sizeof (QUE_Elem)) ;
        HAL_cacheWbInv ((Ptr) &(ctrlPtr->fmDspList), sizeof (ctrlPtr->fmDspList)) ;
        HAL_cacheWbInv ((Ptr) tmpPtr, sizeof (QUE_Elem)) ;

        status = IPS_notify (ID_GPP,
                             mqtState->ipsId,
                             mqtState->ipsEventNo,
                             (Uint16) 0,
                             FALSE) ;

    In implement of IPS_notify(), I found this

                    /* -------------------------------------------------------------
                     * Send an interrupt with the event information to the GPP
                     * -------------------------------------------------------------
                     */
                    HAL_intSend (IPS_object [ipsId].ipsCtrlPtr->config.gppIntId,
                                 eventNo) ;

    Track   HAL_intSend (), finally

    #define MAILBOX_MESSAGE_0      MAILBOX_BASE + 0x40

    Void
    HAL_intSend (Uint32 intId, Uns arg)
    {
        /* To avoid compiler warning. */
        (void) intId ;

        /* Put into the GPP's mailbox to generate the interrupt. */
        REG32(MAILBOX_MESSAGE_0) = arg ;
    }

    MAILBOX_MESSAGE_0   is a mailbox of IPC

    I am not sure about MSGQ flow when using DSP/BIOS LINK, so I got confused. I hope you can give me more advise.

    Thanks,

    Xu

  • Armstrong Xu said:

    Hi Nag,

    Thanks for your help.

    I am not familiar with DSP/BIOS LINK, and I don't know when DSP  sends the message to the reader, how it l informs ARM that "you got a message in your que"?

    Thanks,

    Xu

    Xu,

    When the writer calls the put() API on one processor core, it internally does many things including sending an interrupt (Notification) through the mailbox to the other core, where the reader resides. The message queue module on the reader processor will come to know about the message and which inturn puts the message (pointer) to the readers queue. I hope this answers your question.

    Regards,

    Nag

    (If your question is answered, please click the  Verify Answer  button below)

     

  • Hi Nag,

    "The message module on the reader processor will come to know about the message and which inturn puts the message(pointer) to the readers queue"

    I think the sender will put the header into the reader's queue.

    Thanks for your help, I think by using HWI to handle the Notification and SWI_inc (instead of SWI_post) , software could avoid dropping any MSG in MSGQ.

    Regards.

    Xu

  • Xu,

    You can use the syslink product for communication between processor cores. Syslink is the next generation dsplink.

    The following page also has links to the migration guide, FAQs, User guide, release information.

    http://processors.wiki.ti.com/index.php/Category:SysLink

    Regards,

    Nag