PROCESSOR-SDK-AM64X: Linker Script Issues on AM64x - porting from AM65xx

/*----------------------------------------------------------------------------*/
/* File: linker_r5f_mcu1_0_sysbios.lds                                        */
/* Description:			  					      */
/*    Link command file for Maxwell MCU1_0 view				      */
/*	  TI ARM Compiler version 15.12.3 LTS or later			      */
/*                                                                            */
/* (c) Texas Instruments 2018, All rights reserved.                           */
/*----------------------------------------------------------------------------*/
/*  History:								      */
/*    Aug 26th, 2016 Original version .......................... Loc Truong   */
/*    Aug 01th, 2017 new TCM mem map  .......................... Loc Truong   */
/*    Nov 07th, 2017 Changes for R5F Init Code.................. Vivek Dhande */
/*    Sep 17th, 2018 Added DDR sections for IPC................. J. Bergsagel */
/*    Sep 26th, 2018 Extra mem sections for IPC resource table.. J. Bergsagel */
/*    Nov 06th, 2018 Correction to TCM addresses for MCU1_0..... J. Bergsagel */
/*    Nov 07th, 2018 Split up OCMRAM_MCU for split-mode R5Fs.... J. Bergsagel */
/*----------------------------------------------------------------------------*/
/* Linker Settings                                                            */
/* Standard linker options						      */
--fill_value=0
--stack_size=0x2000
--heap_size=0x1000

-stack  0x2000                              /* SOFTWARE STACK SIZE           */
-heap   0x2000                              /* HEAP AREA SIZE                */

#define DDR0_ALLOCATED_START 0xA0000000
#define OCSRAM_START 0x70000000

#define MCU1_0_EXT_DATA_BASE     	(OCSRAM_START) 			 		/* OCSRAM 0 	: 128kB */
#define MCU1_0_IPC_DATA_BASE     	(OCSRAM_START + 0x00020000)		/* OCSRAM 0 	: 128kB */
#define MCU1_0_R5F_MEM_TEXT_BASE 	(OCSRAM_START + 0x00040000) 	/* OCSRAM 1,2 	: 512kB */
#define MCU1_0_R5F_MEM_DATA_BASE 	(OCSRAM_START + 0x000C0000)		/* OCSRAM 3     : 256kB */
#define MCU1_0_SPACE_BASE    		(OCSRAM_START + 0x00100000)		/* OCSRAM 4,5,6 : 768kB */
#define MCU1_0_RESERVED_SYSFW		(OCSRAM_START + 0x001C0000)		/* OCSRAM 7		: 256kB */

/*
#define MCU1_1_ALLOCATED_START   DDR0_ALLOCATED_START + 0x01000000
#define MCU1_1_EXT_DATA_BASE     (MCU1_1_ALLOCATED_START + 0x00100000)
#define MCU1_1_R5F_MEM_TEXT_BASE (MCU1_1_ALLOCATED_START + 0x00200000)
#define MCU1_1_R5F_MEM_DATA_BASE (MCU1_1_ALLOCATED_START + 0x00300000)
#define MCU1_1_DDR_SPACE_BASE    (MCU1_1_ALLOCATED_START + 0x00400000)

#define MCU2_0_ALLOCATED_START   DDR0_ALLOCATED_START + 0x02000000
#define MCU2_0_EXT_DATA_BASE     (MCU2_0_ALLOCATED_START + 0x00100000)
#define MCU2_0_R5F_MEM_TEXT_BASE (MCU2_0_ALLOCATED_START + 0x00200000)
#define MCU2_0_R5F_MEM_DATA_BASE (MCU2_0_ALLOCATED_START + 0x00300000)
#define MCU2_0_DDR_SPACE_BASE    (MCU2_0_ALLOCATED_START + 0x00400000)

#define MCU2_1_ALLOCATED_START   DDR0_ALLOCATED_START + 0x03000000
#define MCU2_1_EXT_DATA_BASE     (MCU2_1_ALLOCATED_START + 0x00100000)
#define MCU2_1_R5F_MEM_TEXT_BASE (MCU2_1_ALLOCATED_START + 0x00200000)
#define MCU2_1_R5F_MEM_DATA_BASE (MCU2_1_ALLOCATED_START + 0x00300000)
#define MCU2_1_DDR_SPACE_BASE    (MCU2_1_ALLOCATED_START + 0x00400000)
*/
#define ATCM_START 0x00000000
#define BTCM_START 0x41010000

-e __VECS_ENTRY_POINT

/*----------------------------------------------------------------------------*/
/* Memory Map                                                                 */
MEMORY
{
    /* MCU1_R5F_0 local view  */
    MCU_ATCM (RWX)		: origin=ATCM_START	length=0x8000
    /* MCU1_R5F0_TCMB0 (RWIX)	: origin=0x41010000	length=0x8000 (documented only, to avoid conflict below) */

    /* MCU1_R5F_0 SoC view  */
    MCU1_R5F0_ATCM (RWIX)  	: origin=0x41000000 length=0x8000
    MCU1_R5F0_BTCM (RWIX) 	: origin=0x41010000 length=0x8000

    /* from 0x70000000 : 7x 256kB blocks */
    MCU1_0_EXT_DATA  (RWIX)		: origin=MCU1_0_EXT_DATA_BASE     	length=0x00020000	/*   128kB */
    MCU1_0_IPC_DATA (RWIX)		: origin=MCU1_0_IPC_DATA_BASE     	length=0x00020000	/*   128kB */
    
    MCU1_0_R5F_MEM_TEXT (RWIX)	: origin=MCU1_0_R5F_MEM_TEXT_BASE 	length=0x00080000	/*   512kB */
    MCU1_0_R5F_MEM_DATA (RWIX)	: origin=MCU1_0_R5F_MEM_DATA_BASE 	length=0x00040000	/*   256kB */
    MCU1_0_SPACE (RWIX)			: origin=MCU1_0_SPACE_BASE    		length=0x000C0000	/* 3 x 256kB */
    
    
    //DDR0_RESERVED    (RWIX)  	: origin=0x80000000 length=0x20000000	  	/* 512MB */
    //MCU1_1_IPC_DATA (RWIX)	: origin=MCU1_1_ALLOCATED_START   length=0x00100000	/*   1MB */
    //MCU1_1_EXT_DATA  (RWIX)	: origin=MCU1_1_EXT_DATA_BASE     length=0x00100000	/*   1MB */
    //MCU1_1_R5F_MEM_TEXT (RWIX)	: origin=MCU1_1_R5F_MEM_TEXT_BASE length=0x00100000	/*   1MB */
    //MCU1_1_R5F_MEM_DATA (RWIX)	: origin=MCU1_1_R5F_MEM_DATA_BASE length=0x00100000	/*   1MB */
    //MCU1_1_DDR_SPACE (RWIX)	: origin=MCU1_1_DDR_SPACE_BASE    length=0x00C00000	/*  12MB */
    //MCU2_0_IPC_DATA (RWIX)	: origin=MCU2_0_ALLOCATED_START   length=0x00100000	/*   1MB */
    //MCU2_0_EXT_DATA  (RWIX)	: origin=MCU2_0_EXT_DATA_BASE     length=0x00100000	/*   1MB */
    //MCU2_0_R5F_MEM_TEXT (RWIX)	: origin=MCU2_0_R5F_MEM_TEXT_BASE length=0x00100000	/*   1MB */
    //MCU2_0_R5F_MEM_DATA (RWIX)	: origin=MCU2_0_R5F_MEM_DATA_BASE length=0x00100000	/*   1MB */
    //MCU2_0_DDR_SPACE (RWIX)	: origin=MCU2_0_DDR_SPACE_BASE    length=0x00C00000	/*  12MB */
    //MCU2_1_IPC_DATA (RWIX)	: origin=MCU2_1_ALLOCATED_START   length=0x00100000	/*   1MB */
    //MCU2_1_EXT_DATA  (RWIX)	: origin=MCU2_1_EXT_DATA_BASE     length=0x00100000	/*   1MB */
    //MCU2_1_R5F_MEM_TEXT (RWIX)	: origin=MCU2_1_R5F_MEM_TEXT_BASE length=0x00100000	/*   1MB */
    //MCU2_1_R5F_MEM_DATA (RWIX)	: origin=MCU2_1_R5F_MEM_DATA_BASE length=0x00100000	/*   1MB */
    //MCU2_1_DDR_SPACE (RWIX)	: origin=MCU2_1_DDR_SPACE_BASE    length=0x00C00000	/*  12MB */

    //SHARED_DDR_SPACE (RWIX)	: origin=0xA5000000 length=0x00800000           /*  8MB */

}  /* end of MEMORY */

/*----------------------------------------------------------------------------*/
/* Section Configuration                                                      */

SECTIONS
{
    .vecs       : {
        __VECS_ENTRY_POINT = .;
    } palign(8) > ATCM_START
    .init_text  : {
                     boot.*(.text)
                     *(.text:ti_sysbios_family_arm_MPU_*)
                     *(.text:ti_sysbios_family_arm_v7r_Cache_*)
                  }  > MCU_ATCM
    .text:xdc_runtime_Startup_reset__I : {} palign(8) > MCU_ATCM
    .text		: {} palign(8)    	> MCU1_0_R5F_MEM_TEXT
    .cinit   	: {} palign(8) 		> MCU1_0_R5F_MEM_TEXT
    .pinit   	: {} palign(8) 		> MCU1_0_R5F_MEM_TEXT
    .const   	: {} palign(8) 		> MCU1_0_R5F_MEM_DATA
    .bss     	: {} align(4)  		> MCU1_0_SPACE
    .data    	: {} palign(128) 	> MCU1_0_SPACE
    .data_buffer: {} palign(128) 	> MCU1_0_SPACE
    .sysmem  	: {} 			> MCU1_0_SPACE
    .stack	: {} align(4)		> MCU1_0_SPACE
    .init_array	: {} palign(8) 		> MCU1_0_IPC_DATA
    
    ipc_data_buffer (NOINIT) : {} palign(128)	> MCU1_0_IPC_DATA
    .resource_table : {
        __RESOURCE_TABLE = .;
    } > MCU1_0_EXT_DATA

    .tracebuf   : {}			> MCU1_0_EXT_DATA

}  /* end of SECTIONS */

/*----------------------------------------------------------------------------*/
/* Misc linker settings                                                       */


/*-------------------------------- END ---------------------------------------*/

/* =============================================================================
 *   Copyright (c) 2018, Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
var Types = xdc.useModule("xdc.runtime.Types");
var Defaults = xdc.useModule('xdc.runtime.Defaults');
var Diags = xdc.useModule('xdc.runtime.Diags');
var Error = xdc.useModule('xdc.runtime.Error');
var Log = xdc.useModule('xdc.runtime.Log');
var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
var Main = xdc.useModule('xdc.runtime.Main');
var Memory = xdc.useModule('xdc.runtime.Memory')
var System = xdc.useModule('xdc.runtime.System');
var Text = xdc.useModule('xdc.runtime.Text');
var Clock = xdc.useModule('ti.sysbios.knl.Clock');
var Task = xdc.useModule('ti.sysbios.knl.Task');
var Event = xdc.useModule('ti.sysbios.knl.Event');
var Mailbox = xdc.useModule('ti.sysbios.knl.Mailbox');
var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
var HeapMin = xdc.useModule('xdc.runtime.HeapMin');
var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
var GateMutex = xdc.useModule('ti.sysbios.gates.GateMutex');

var BIOS = xdc.useModule('ti.sysbios.BIOS');
var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
var Core = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Core');
var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
var SysMin = xdc.useModule('xdc.runtime.SysMin');
var Timer = xdc.useModule('ti.sysbios.hal.Timer');




/* Enable cache */
var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
Cache.enableCache = true;

/*
 * Direct CIO to UART
 */
/* System.SupportProxy = SysUart; */

System.SupportProxy = SysMin;
System.extendedFormats += "%f";

/* 
 * Program.argSize sets the size of the .args section. 
 * The examples don't use command line args so argSize is set to 0.
 */
Program.argSize = 0x0;

/*
 * Uncomment this line to globally disable Asserts.
 * All modules inherit the default from the 'Defaults' module.  You
 * can override these defaults on a per-module basis using Module.common$. 
 * Disabling Asserts will save code space and improve runtime performance.
Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
 */

/*
 * Uncomment this line to keep module names from being loaded on the target.
 * The module name strings are placed in the .const section. Setting this
 * parameter to false will save space in the .const section.  Error and
 * Assert messages will contain an "unknown module" prefix instead
 * of the actual module name.
Defaults.common$.namedModule = false;
 */

/* Create default heap and hook it into Memory 
 * We use the HeapMin-implementation because we never free any memory
 * and just create objects at startup.
 * other dynamic-memory-creation shall use memory-pools/allocators like tlsf
 */
var heapMinParams = new HeapMin.Params;
heapMinParams.size = 16384*4;
var heap0 = HeapMin.create(heapMinParams);

Memory.defaultHeapInstance = heap0;

Defaults.common$.memoryPolicy = Types.CREATE_POLICY;

/*
 * Minimize exit handler array in System.  The System module includes
 * an array of functions that are registered with System_atexit() to be
 * called by System_exit().
 */
System.maxAtexitHandlers = 4;       

/* 
 * Uncomment this line to disable the Error print function.  
 * We lose error information when this is disabled since the errors are
 * not printed.  Disabling the raiseHook will save some code space if
 * your app is not using System_printf() since the Error_print() function
 * calls System_printf().
Error.raiseHook = null;
 */

/* 
 * Uncomment this line to keep Error, Assert, and Log strings from being
 * loaded on the target.  These strings are placed in the .const section.
 * Setting this parameter to false will save space in the .const section.
 * Error, Assert and Log message will print raw ids and args instead of
 * a formatted message.
Text.isLoaded = false;
 */

/*
 * Uncomment this line to disable the output of characters by SysMin
 * when the program exits.  SysMin writes characters to a circular buffer.
 * This buffer can be viewed using the SysMin Output view in ROV.
SysMin.flushAtExit = false;
 */

/* 
 * The BIOS module will create the default heap for the system.
 * Specify the size of this default heap.
 *
 * BIOS.heapSize = 0x2000; */

/* System stack size (used by ISRs and Swis) */
Program.stack = 0x4000;

Task.defaultStackSize = 0x4000;
Task.common$.namedInstance = true;
Task.common$.namedModule = true;

var devType              = java.lang.System.getenv("SOC");
var boardName            = java.lang.System.getenv("BOARD");
var buildType 			 =  java.lang.System.getenv("BUILD_PROFILE");
var coreId = java.lang.System.getenv("CORE");
print(coreId);

var Csl         		 = xdc.loadPackage('ti.csl');
Csl.Settings.deviceType  = devType;
Csl.Settings.libProfile  = buildType;


// Load the SCICLIENT package
var SciClient    		       = xdc.loadPackage('ti.drv.sciclient');
SciClient.Settings.socType     = devType;
SciClient.Settings.boardType   = boardName;
SciClient.Settings.coreType    = coreId;
SciClient.Settings.libProfile  = buildType;


/* Load the OSAL package */
var osType = "tirtos"
var Osal = xdc.useModule('ti.osal.Settings');
Osal.osType = osType;
Osal.socType = devType;

var Board = xdc.loadPackage('ti.board');
Board.Settings.boardName = boardName;
Board.Settings.libProfile  = buildType;

// load uart package
var Uart              = xdc.loadPackage('ti.drv.uart');
Uart.Settings.socType = devType;
Uart.Settings.libProfile  = buildType;

// load gpio package
var Gpio              = xdc.loadPackage('ti.drv.gpio');
Gpio.Settings.socType = devType;
Gpio.Settings.libProfile  = buildType;

// load spi package
var Spi              = xdc.loadPackage('ti.drv.spi');
Spi.Settings.socType = devType;
Spi.Settings.libProfile  = buildType;

// load i2c package
var I2c              = xdc.loadPackage('ti.drv.i2c');
I2c.Settings.socType = devType;
I2c.Settings.libProfile  = buildType;

// load dma package
var Udma              = xdc.loadPackage('ti.drv.udma');
Udma.Settings.socType = devType;
Udma.Settings.libProfile  = buildType;


/* 
 * Create and install logger for the whole system
 */
var loggerBufParams = new LoggerBuf.Params();
loggerBufParams.numEntries = 32;
var logger0 = LoggerBuf.create(loggerBufParams);
Defaults.common$.logger = logger0;
Main.common$.diags_INFO = Diags.ALWAYS_ON;

BIOS.libType = BIOS.LibType_Custom;
BIOS.cpuFreq.lo = 800000000;
BIOS.cpuFreq.hi = 0;




/* Disable Timer frequency check, workaround for QT test */
var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
Timer.checkFrequency = false;

for (var i = 0; i < 4; i++) {
    Timer.intFreqs[i].lo = 25000000;
    Timer.intFreqs[i].hi = 0;
}


Clock.timerId = 1;


if(coreId=="mcu1_0")
{
    Core.id = 0;
    /* DM timer cfg */
    Clock.timerId = 0;
}
if(coreId=="mcu1_1")
{
    Core.id = 1;
    /* DM timer cfg */
    Clock.timerId = 1;
}
if(coreId=="mcu2_0")
{
    Core.id = 0;
    Clock.timerId = 2;
}
if(coreId=="mcu2_1")
{
    Core.id = 1;
    Clock.timerId = 3;
}
/* Sysbios supports workaround for Silicon issue https://jira.itg.ti.com/browse/K3_OPEN_SI-148
 * Details of silicon issue : https://confluence.itg.ti.com/display/PROCIPDEV/%2310+The+same+interrupt+cannot+be+nested+back-2-back+within+another+interrupt
 * Sysbios Requirement Details: https://jira.itg.ti.com/browse/SYSBIOS-1419
 * Workaround requires use of a resevred dummyIRQ.
 * Using DummyIRQ#383 as per cslr_intr_mss.h it is a reserved interrupt not connected to any
 * peripheral interrupt sources
 */
//Hwi.dummyIRQ                   = 255;

//var Reset = xdc.useModule("xdc.runtime.Reset");
//Reset.fxns[Reset.fxns.length++] = "&utilsCopyVecs2ATcm";

/*
 * Initialize MPU and enable it
 *
 * Note: MPU must be enabled and properly configured for caching to work.
 */
xdc.loadCapsule("r5_mpu.xs");

//var Load = xdc.useModule('ti.sysbios.utils.Load');

/* load calculation related settings */
//Load.swiEnabled   = true;
//Load.hwiEnabled   = true;
//Load.taskEnabled  = true;
//Load.updateInIdle = false;

/* Check if application needs to update with custom configuration options */
/* Caution: This should be at the end of this file after all other common cfg */
var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
if ((cfgUpdate != '')&&(cfgUpdate != null))
{
    xdc.print("Loading configuration update " + cfgUpdate);
    xdc.loadCapsule(cfgUpdate);
}

/*
 * Copyright (c) 2020, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

//
//File Name: launch_am64x.js
//Description:
//   Launch the DMSC firmware and board configuration from R5F.
//
//Usage:
//
//From CCS Scripting console
//  1. loadJSFile "C:\\ti\\launch_am64x.js"
//
//Note:
//  1. Search for "edit this" to look at changes that need to be edited
//     for your usage.
//


//<!!!!!! EDIT THIS !!!!!>
// Set this to 1 to allow loading the GEL files directly from the ccxml file.
disableGelLoad = 0;
// Set to 1 to use the firmware with Firewalls.
if (disableGelLoad == 0)
{
    //Path to GEL files
    gelFilePath = "./ti/ccs1020/ccs/ccs_base/emulation/gel/AM64x";
}
//PDK path. Edit this
pdkPath = "./ti/processor_sdk_sitara_am64x_00_09_00_01/rtos/pdk_am64x_07_01_03_09";

//path to board config elf
ccs_init_elf_file = pdkPath+"/packages/ti/drv/sciclient/tools/ccsLoadDmsc/am64x/sciclient_ccs_init_mcu1_0_release.xer5f";

//path to sysfw bin
sysfw_bin = pdkPath+"/packages/ti/drv/sciclient/soc/sysfw/binaries/ti-sci-firmware-am64x-gp.bin"

//<!!!!!! EDIT THIS !!!!!>

// Import the DSS packages into our namespace to save on typing
importPackage(Packages.com.ti.debug.engine.scripting)
importPackage(Packages.com.ti.ccstudio.scripting.environment)
importPackage(Packages.java.lang)
importPackage(java.io);
importPackage(java.lang);

function updateScriptVars()
{
    //Open a debug session
    dsMCU1_0 = debugServer.openSession( ".*MAIN_Cortex_R5_0_0" );
    dsDMSC_0 = debugServer.openSession( ".*DMSC_Cortex_M3_0" );
}

function printVars()
{
    updateScriptVars();
}

function connectTargets()
{
    /* Set timeout of 20 seconds */
    script.setScriptTimeout(200000);
    updateScriptVars();
    // On VLAB the sys reset is not present. This will be required post silicon
    //sysResetVar=dsDMSC_0.target.getResetType(1);
    //sysResetVar.issueReset();

    print("Connecting to DMSC_Cortex_M3_0!");
    // Connect targets
    dsDMSC_0.target.connect();
    /* Init M4F. WFI Vector set into IRAM to avoid hard fault */
    dsDMSC_0.expression.evaluate("Init_M4()");
    /* TODO: This will be required when the GEL files are done which does the R5F
     * RAT Mapping.
     */
    print("Fill R5F ATCM memory...");
    dsDMSC_0.memory.fill(0x78000000, 0, 0x2000, 0);
    print("Writing While(1) for R5F")
    dsDMSC_0.memory.writeWord(0, 0x78000000, 0xE59FF004); /* ldr        pc, [pc, #4] */
    dsDMSC_0.memory.writeWord(0, 0x78000004, 0x38);       /* Address 0x38 */
    dsDMSC_0.memory.writeWord(0, 0x78000038, 0xEAFFFFFE) /* b          #0x38 */

    /* RAT Config for OCSRAM SYSFW load */
    dsDMSC_0.memory.writeWord(0, 0x44200024, 0x00060000);
    dsDMSC_0.memory.writeWord(0, 0x44200028, 0x44060000);
    dsDMSC_0.memory.writeWord(0, 0x4420002C, 0x00000000);
    dsDMSC_0.memory.writeWord(0, 0x44200020, 0x80000011);

    dsDMSC_0.memory.writeWord(0, 0x44200034, 0x00080000);
    dsDMSC_0.memory.writeWord(0, 0x44200038, 0x44080000);
    dsDMSC_0.memory.writeWord(0, 0x4420003C, 0x00000000);
    dsDMSC_0.memory.writeWord(0, 0x44200030, 0x80000011);

    dsDMSC_0.memory.writeWord(0, 0x44200044, 0x60000000);
    dsDMSC_0.memory.writeWord(0, 0x44200048, 0x40000000);
    dsDMSC_0.memory.writeWord(0, 0x4420004C, 0x00000000);
    dsDMSC_0.memory.writeWord(0, 0x44200040, 0x8000001D);

    dsDMSC_0.memory.writeWord(0, 0x44200054, 0x80000000);
    dsDMSC_0.memory.writeWord(0, 0x44200058, 0x00000000);
    dsDMSC_0.memory.writeWord(0, 0x4420005C, 0x00000000);
    dsDMSC_0.memory.writeWord(0, 0x44200050, 0x8000001D);

    print("Loading DMSC Firmware ... " + sysfw_bin);
    // Load the DMSC firmware
    dsDMSC_0.memory.loadRaw(0, 0x44000, sysfw_bin, 32, false);
    print("DMSC Firmware Load Done...");
    // Set Stack pointer and Program Counter
    stackPointer = dsDMSC_0.memory.readWord(0, 0x44000);
    progCounter = dsDMSC_0.memory.readWord(0, 0x44004);
    dsDMSC_0.memory.writeRegister("SP", stackPointer);
    dsDMSC_0.memory.writeRegister("PC", progCounter);
    print( "DMSC Firmware run starting now...");
    // Run the DMSC firmware
    dsDMSC_0.target.runAsynch();
    print("Connecting to MCU Cortex_R5_0!");

    // Connect the MCU R5F
    dsMCU1_0.target.connect();

    // This is done to support other boot modes. OSPI is the most stable.
    // MMC is not always stable.
    bootMode = dsMCU1_0.memory.readWord(0, 0x43000030) & 0x78;
    print (" Main Boot Mode is " + bootMode);
    if (bootMode != 0x78)
    {
        print("Disable MCU Timer for ROM clean up");
        dsMCU1_0.memory.writeWord(0, 0x002400010, 0x1); /* Write reset to MCU Timer 0. Left running by ROM */
        dsMCU1_0.memory.writeWord(0, 0x2FFF0430, 0xFFFFFFFF); /* Clear Pending Interrupts */
        dsMCU1_0.memory.writeWord(0, 0x2FFF0018, 0x0); /* Clear Pending Interrupts */
        // Reset the R5F to be in clean state.
        dsMCU1_0.target.reset();
        // Load the board configuration init file.
        dsMCU1_0.expression.evaluate('GEL_Load("'+ ccs_init_elf_file +'")');
        // Run Asynchronously
        dsMCU1_0.target.runAsynch();
        print ("Running Async");
        // Halt the R5F and re-run.
        dsMCU1_0.target.halt();
    }

    // Halt the R5F and re-run.
    dsMCU1_0.target.halt();

    // Reset the R5F and run.
    dsMCU1_0.target.reset();

    print("Running the board configuration initialization from R5!");
    // Load the board configuration init file.
    dsMCU1_0.memory.loadProgram(ccs_init_elf_file);
    // Halt the R5F and re-run.
    dsMCU1_0.target.halt();
    // Run Synchronously for the executable to finish
    dsMCU1_0.target.run();

    /* Run the DDR Configuration */
    // print("Running the DDR configuration... Wait till it completes!");
    // dsMCU1_0.target.halt();
    // dsMCU1_0.expression.evaluate("AM64_DDR_Initialization_ECC_Disabled()");
}

function disconnectTargets()
{
    updateScriptVars();
    // Reset the R5F to be in clean state.
    dsMCU1_0.target.reset();
    // Disconnect targets
    dsDMSC_0.target.disconnect();
}

function sampleDDRCheck ()
{
    print("Running DDR Memory Checks....");
    dsMCU1_0.memory.fill (0x80000000, 0, 1024, 0xA5A5A5A5);
    ar = dsMCU1_0.memory.readWord(0, 0x80000000, 1024);
    fail = 0
    for (i = 0; i < ar.length; i++) {
            x = ar[i];
            if (x != 0xA5A5A5A5)
            {
                fail = 1;
            }
        }
    if (fail == 1)
    {
        print ("0x80000000: DDR memory sample check failed !!");
    }
    dsMCU1_0.memory.fill (0x81000000, 0, 1024, 0x5A5A5A5A);
    ar = dsMCU1_0.memory.readWord(0, 0x81000000, 1024);
    fail = 0
    for (i = 0; i < ar.length; i++) {
            x = ar[i];
            if (x != 0x5a5a5a5a)
            {
                fail = 1;
            }
        }
    if (fail == 1)
    {
        print ("0x81000000: DDR memory sample check failed !!");
    }
}

function doEverything()
{
    printVars();
    connectTargets();
    disconnectTargets();
    //sampleDDRCheck ();
    print("Happy Debugging!!");
}

var ds;
var debugServer;
var script;

// Check to see if running from within CCSv4 Scripting Console
var withinCCS = (ds !== undefined);

// Create scripting environment and get debug server if running standalone
if (!withinCCS)
{
    // Import the DSS packages into our namespace to save on typing
    importPackage(Packages.com.ti.debug.engine.scripting);
    importPackage(Packages.com.ti.ccstudio.scripting.environment);
    importPackage(Packages.java.lang);

    // Create our scripting environment object - which is the main entry point into any script and
    // the factory for creating other Scriptable ervers and Sessions
    script = ScriptingEnvironment.instance();

    // Get the Debug Server and start a Debug Session
    debugServer = script.getServer("DebugServer.1");
}
else // otherwise leverage existing scripting environment and debug server
{
    debugServer = ds;
    script = env;
}

doEverything();