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AM5726: Setting DDR Addresses for Each Core

Kanae
Guru 10245 points

Part Number: AM5726
Other Parts Discussed in Thread: SYSBIOS

Hi Sitara support Team,

 

When running a program in CCS, how do I load the executable program for each CPU (ARM, DSP, IPU) to the specified address in DDR?

 

Q1: In the PDK sample program, the load address for each core is shown below.
       Please tell me where to specify the address and how to change it arbitrarily.

 

A15: 0x80000000 - ...

C66: 0x84000000 - ...

M4: 0x81000000 - ...

 

Q2: Also, is it correct that the .bld files for each core in the following directory are required for the TI_RTOS build,
      although this does not seem to be reflected in the actual sample project?

 

C:\pdk_am57xx_x_xx_xx_xx\packages\ti\build\am572x

 

 

Q3．If yes, are the following settings in the *.bld file (e.g. config_am572x_a15.bld) required?

 

 APP_CACHED_DATA_SIZE = 20*MB;

 APP_CACHED_DATA_BLK1_SIZE = 244*MB;

 APP_CACHED_DATA_BLK2_SIZE = 128*MB;

 APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;

 

Q4. Since the customer plans to use 512M DDR3, is it possible to reduce the size to an arbitrary size?

For example,

 APP_CACHED_DATA_SIZE = 10*MB;

 APP_CACHED_DATA_BLK1_SIZE = 122*MB;

 APP_CACHED_DATA_BLK2_SIZE = 64*MB;

 APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;

 

If you need the additional information to reply, please let me know.

Best regards,
Kanae

  • 0
    Guru 10245 points

    Hi,

    The question is related to customer's device selection and needs to be answered this week.
    If you have difficulty answering, please reply with only a response schedule.

    Thank you for your support.

    Best regards,
    Kanae

  • 0
    TI__Guru 50045 points

    Hi,

    Q1: Memory map is specified in *.bld file for RTOS build. Baremetal projects in CSL have their own linker command file. It depends on examples.

    Q2: Yes. *.bld is used for RTOS build. Which sample project does not match the definition in *.bld?

    Q3: It might be required for some samples. Refer to *.cfg file for the sample project. Not every sample uses every memory section.

    Q4: Customer can define the section based on their needs. They don't have to follow the exact memory section definition used by sample.

    For multi-core usage with A15/C66x/M4, customer can define the memory map similar to  ~/pdk_am57xx_1_0_17/packages/ti/build/am572x/mem_segment_definition_1024mb_bios.xs as a reference.

    Regards,

    Stanley

  • 0 in reply to Stanley Liu
    Intellectual 930 points

    Hi,Stanley

    Thenk you for Reply.
    I'm Hidekazu, who belongs to the same department as Kanae.
    From here, I will be in charge.

    Q1: Memory map is specified in *.bld file for RTOS build. Baremetal projects in CSL have their own linker command file. It depends on examples.
    >
    ---
    I understand that it is specified in the bld file, but the load address setting part of DDR in Config_am574x.bld / Config_am574x_a15.bld / Config_am574x_c66.bld has the same value.

    Please tell me the specific setting location and change method.

    /* First 4KB reserved for components such as SBL */
    SBL_SIZE = 4*KB;
    DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
    DDR3_ADDR_1 = 0xA0000000;

    Q2: Yes. *.bld is used for RTOS build. Which sample project does not match the definition in *.bld?
    >
    ---
    An example that does not match .bld is GPIO_LedBlink_idkAM574x_armTestProject.
    Where does this sample code set the .bld file?

    Q4: Customer can define the section based on their needs. They don't have to follow the exact memory section definition used by sample.

    For multi-core usage with A15/C66x/M4, customer can define the memory map similar to ~/pdk_am57xx_1_0_17/packages/ti/build/am572x/mem_segment_definition_1024mb_bios.xs as a reference.
    >
    ---
    The customer wants to use 512MB of DDR instead of 1024MB to configure a working memory MAP with the minimum required configuration.

    In this setting example, a setting example of 1024MB is given. Is this the minimum required configuration?
    If I choose 512MB DDR, will it cause problems or instability?

    Also, please tell me the recommended setting example (equivalent to mem_segment_definition_512mb_bios.xs) when using 512MB?


    Best Regards,
    Hidekazu

  • 0 in reply to Hidekazu
    TI__Guru 50045 points

    Hi Hidekazu,

    Hidekazu said:

    Please tell me the specific setting location and change method.

    /* First 4KB reserved for components such as SBL */
    SBL_SIZE = 4*KB;
    DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
    DDR3_ADDR_1 = 0xA0000000;

    Q1: The OCMC_RAM and DDR memory segment should be defined in the same way in *.bld files for all targets, i.e. A15/C66x/M4. This way you can avoid conflict from different targets accessing DDR. The internal memory segments like L1, L2 memory would be different for each target since it is CPU specific.

    Finally, for each target, you will assign the code and data sections to different memory segments in the *.cfg file of the target.

    PDK doesn't provide example for multi-core application so it is not a good reference for that.

    I would recommend you to review IPC release, ~\ipc_3_50_04_08.

    https://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_Foundational_Components.html#ipc-user-s-guide

    Hidekazu said:
    An example that does not match .bld is GPIO_LedBlink_idkAM574x_armTestProject.
    Where does this sample code set the .bld file?

    Q2: These CCS example projects created by the PDK script are set up differently than the PDK example projects built with makefile in command-line window. For example, the linker command file used by GPIO_LedBlink_idkAM574x_armTestProject is auto-generated based on the memory definition in SYSBIOS.

    With CPU set to A15, it takes the inputs from ~\bios_6_76_03_01\packages\ti\catalog\arm\cortexa15\DRA7XX.xdc.

    With Platform set to idkAM574x, it also takes the input from ~\bios_6_76_03_01\packages\ti\platforms\idkAM572X\Platform.xdc.

    And, finally, it generates ~\pdk_am57xx_1_0_17\packages\MyExampleProjects\GPIO_LedBlink_idkAM574x_armTestProject\Release\configPkg\linker.cmd to be used in the build.

    This is way too complicated for a simple project build setup so I wouldn't recommend you to follow this. This is only meant for standalone example project to run some quick tests on the EVM.

    I would recommend you to use makefile based build from command-line than building in CCS with CCS project.

    Hidekazu said:
    In this setting example, a setting example of 1024MB is given. Is this the minimum required configuration?
    If I choose 512MB DDR, will it cause problems or instability?

    As mentioned earlier, it is just an example. You can modify the size to fit 512MB.

  • 0 in reply to Stanley Liu
    Intellectual 930 points

    Hi,Stanley
    Thank you for the useful information.


    The customer is tuning the bld file,
    When is the following cache-related setting value (3 SIZE) required?
    I would like you to explain the specific purpose of use and whether it is necessary or not.

    APP_CACHED_DATA_BLK1_SIZE = 122*MB;
    APP_CACHED_DATA_BLK2_SIZE = 64*MB;
    APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;

    Best Regards、
    Hidekazu

  • 0 in reply to Hidekazu
    Intellectual 930 points

    Hi,Stanley

    Since there is no answer, I posted a new post in the following thread.

    e2e.ti.com/.../am572x-bld-configuration-parameters

    Best Regards,
    Hidekazu

  • 0 in reply to Hidekazu
    TI__Guru 50045 points

    Sorry, I will reply to the other thread and close this one.