How to change the SPI PIN config for 8168?

Hi Strachey,

Strachey said:

As told in sprugx8b

The latest DM816x TRM is SPRUGX8C – March 2015

Strachey said:

How can i config SPI_D[0] as MOSI?

You need to set PINCTRL171 [2:0] MUXMODE = 0 and config McSPI_CH[i]CONF register.

BR
Pavel

Hi Pavel,

    Thanks for your reply!

    I do as the User Guide told that add specific mux entry in board_mux array in arch/arm/mach-omap2/board-ti8168evm.c like "TI816X_MUX(TI816X_CONTROL_PADCONF_SPI_D0_OFFSET, OMAP_MUX_MODE0|OMAP_PULL_UP), /* SPI_D[0] */"

, but I do not know which mode I need to choose.

    If SPI_D0 is MOSI and SPI_D1 is MISO by default using mode_0 pin multiplexing, now I want to set SPI_D0 as MISO and SPI_D1 as MOSI, how could I choose the pin multiplexing mode and how to choose wether pull up or down?

Thanks Sincerely！

Best Regards！

Strachey,

If we assume that DM816x device is the master, then to configure SPI_D[0] as MISO, and SPI_D[1] as MOSI, you should select OMAP_MUX_MODE0 in both cases (PINCTRL171/172 [2:0] MUXMODE = 0). There is no need for pull resistor for the SPI_D[0] and SPI_D[1] pins, nor pull up, neither pull down. The below entry should be enough:

TI816X_MUX(SPI_D0, OMAP_MUX_MODE0)
TI816X_MUX(SPI_D1, OMAP_MUX_MODE0)

Then you should configure MISO, MOSI and other things from the McSPI registers.

BR
Pavel

Thanks Pavel!

What do you mean "other things from the McSPI registers."? Where could I do with them?

Best Regards!

Hi,

What I mean is to do the right configurations for your use case in the McSPI registers.

BR
Pavel

Pavel,
In my opinion, if DM816x device is the master, whether SPI_D[0] is as MISO or MOSI, the wirte 、read and iocontrol operations are the same in the user's app, is that right? According to my understanding, the configurations are just to set the bitrates、polarity、phase and so on which can be the same as the SPI_D[0] is as MOSI, right ?

Thanks!
Best regards!

Strachey,

To configure SPI_D[0] as MISO, MCSPI_CH(i)CONF[18] IS should be 0.

See DM816x TRM, sections
16.2.3.1 Dedicated Resources Per Channel,
16.3.12 McSPI Channel (i) Configuration Register (MCSPI_CH(i)CONF),
Table 16-33. Data Lines Configurations

BR
Pavel

Dear Pavel,

Thank you so much!

Forgive me, I am a newer for kernel. Could you tell me in DVRRDK_04.00.00.03, which files to be modified can realize?

Sincerely!

Best Regards!

Strachey,

I am not familiar with DVR RDK, I am working with EZSDK. For DVR RDK specific questions you should contact you local TI FAE.

DVR RDK should be based on PSP, as EZSDK. In PSP, there is u-boot and linux kernel. From what I understand, you need to know where in PSP linux kernel is the McSPI driver with its registers.

See the below wiki page for McSPI driver info:
processors.wiki.ti.com/.../TI81XX_PSP_McSPI_Driver_User_Guide

The McSPI driver with registers is located at:
linux-kernel/drivers/spi/omap2-mcspi.c

More McSPI related code is located at:
linux-kernel/arch/arm/mach-omap2/board-ti8168evm.c
linux-kernel/arch/arm/mach-omap2/devices.c

BR
Pavel

Pavel,

        Also in RDK, I modied the function spi_claim_bus in the file uboot/u-boot-dvr-rdk/drivers/spi/omap3_spi.c like :

#if 0
conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
conf |= OMAP3_MCSPI_CHCONF_DPE0;
#else
conf &= ~(OMAP3_MCSPI_CHCONF_DPE0);
conf |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
#endif 

    And I added the pin mux in board_mux array in the file linux-kernel/arch/arm/mach-omap2/board-ti8168evm.c like:

TI816X_MUX(TI816X_CONTROL_PADCONF_SPI_SCLK_OFFSET, OMAP_MUX_MODE0), /* SPI_SCLK */
TI816X_MUX(TI816X_CONTROL_PADCONF_SPI_D0_OFFSET, OMAP_MUX_MODE0), /* SPI_D[0] is as MISO*/
TI816X_MUX(TI816X_CONTROL_PADCONF_SPI_D1_OFFSET, OMAP_MUX_MODE0), /* SPI_D[1] is as MOSI*/

    It did not work, SPI_D[0] was not set as MISO. Did I miss some steps?

Thanks!

Best Regards!

Strachey,

Strachey said:

And I added the pin mux in board_mux array in the file linux-kernel/arch/arm/mach-omap2/board-ti8168evm.c

Are you using DM816x TI EVM? Link to this EVM is below:

If you not using EVM but DVR board, you can try with the below file (instead of board-ti8168evm.c):

linux-kernel/arch/arm/mach-omap2/board-ti8168dvr.c

Strachey said:

TI816X_MUX(TI816X_CONTROL_PADCONF_SPI_SCLK_OFFSET, OMAP_MUX_MODE0), /* SPI_SCLK */
TI816X_MUX(TI816X_CONTROL_PADCONF_SPI_D0_OFFSET, OMAP_MUX_MODE0), /* SPI_D[0] is as MISO*/
TI816X_MUX(TI816X_CONTROL_PADCONF_SPI_D1_OFFSET, OMAP_MUX_MODE0), /* SPI_D[1] is as MOSI*/

The names of multiplexed signals are specified in arch/arm/mach-omap2/mux81xx.c file in kernel source directory. Can you try with the below mux entries:

TI816X_MUX(SPI_SCLK,OMAP_MUX_MODE0)
TI816X_MUX(SPI_D0, OMAP_MUX_MODE0)
TI816X_MUX(SPI_D1, OMAP_MUX_MODE0)

Strachey said:

  It did not work, SPI_D[0] was not set as MISO.

What do you mean by not work? How you define SPI_D[0] was not set as MISO?

BR
Pavel

Pavel,

    1、I am using my board which is almost like EVM, and using board-ti8168evm.c

2、It could not complie if change as you said below.

TI816X_MUX(SPI_SCLK,OMAP_MUX_MODE0)
TI816X_MUX(SPI_D0, OMAP_MUX_MODE0)
TI816X_MUX(SPI_D1, OMAP_MUX_MODE0)

    3、what  I mean is that I do the changes as what I said above, but SPI_D[0] was not set as MISO, it is still MOSI.

Thanks!

Best regards!

Strachey said:

2、It could not complie if change as you said below.

TI816X_MUX(SPI_SCLK,OMAP_MUX_MODE0)
TI816X_MUX(SPI_D0, OMAP_MUX_MODE0)
TI816X_MUX(SPI_D1, OMAP_MUX_MODE0)

Do you have the below code in your linux kernel?

linux-dvr-rdk-dm81xx/arch/arm/mach-omap2/mux81xx.c

_TI816X_MUXENTRY(SPI_SCLK, 0,
        "spi_sclk", NULL, NULL, NULL,
        NULL, NULL, NULL, NULL),

_TI816X_MUXENTRY(SPI_D0, 0,
        "spi_d0", NULL, NULL, NULL,
        NULL, NULL, NULL, NULL),
    _TI816X_MUXENTRY(SPI_D1, 0,
        "spi_d1", NULL, NULL, NULL,
        NULL, NULL, NULL, NULL),

Can you try with the latest DM816x DVR RDK linux kernel code base available at the below link.

Strachey said:

what  I mean is that I do the changes as what I said above, but SPI_D[0] was not set as MISO, it is still MOSI.

Do you mean MCSPI_CH(i)CONF[18] IS == 1?

BR
Pavel