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[FAQ] PROCESSOR-SDK-J721E: How to change lane speed and number of lanes for DSI output?

Brijesh Jadav
Guru**** 433145 points
Part Number: PROCESSOR-SDK-J721E

This article explains how to change number of lanes and lane speed output for the DSI output on TDA4xVM/J721E.

  • 0
    TI__Guru**** 433145 points

    DSI Display driver in PDK supports changing the number of output lanes. This can be changed in the numOfLanes variable of Dss_DctrlDsiParams structure.

    Output Lane Speed is dependent on three parameters, so in order to change lane speed, three parameters are needed to be changed.

    1. Input Divisor: PLL input divider value The value of this signal is used to specify how much the PLL reference clock is divided by at the input to the PLL and is dependent on the input reference clock, which on EVM, by default, set to OFC crystal frequency which is 19.2MHz. Based on the clock frequency, 
      1. Div by 1 if refer clock value is between 9.6MHz to 19.2MHz range
      2. Div by 2, if refer clock value is between 19.2MHz to 38.4MHz range 
      3. Div by 4, if refer clock value is between 38.4MHz to 76.8MHz range 
      4. Div by 8, if refer clock value is between 76.8MHz to 150MHz range 
    2. Output Divisor: PLL output divider value is used to specify how much the PLL output clock is divided by to create the high speed data clock. It is specified as function of required output data rate ie lane speed. Note that the accuracy of the specified data rate is +/- 5 Mbp
      1. Div by 1, if lane speed is in between 2.5 Gbps to 1.25Gbps range
      2. Div by 2, if lane speed is in between 1.24 Gbps to  630Mbps range
      3. Div by 4, if lane speed is in between 620 Mbps to 320Mbps range
      4. Div by 8, if lane speed is in between 310 Mbps to 160Mbps range
      5. Div by 16, if lane speed is in between 150Mbps to 80Mbps range
    3. Feedback Divisor: PLL feedback divider value of this signal specifies the feedback divider value for the PLL. The following equation specifies how to calculate the value that must be driven on this signal.
      1. Feedback divider value = CEIL
        ((lane speed * 2 * output_divisor * input_divisor) / PLL reference clock frequency

    Attached patch adds support for calculating above parameters in the DSS display driver. It adds a new parameter laneSpeedInKbps in Dss_DctrlDsiParams for providing lane speed in terms of Kbps and calculates above parameters for the DSI outputs.

    /cfs-file/__key/communityserver-discussions-components-files/791/Added_5F00_Support_5F00_For_5F00_lane_5F00_speed_5F00_in_5F00_DSI_5F00_Driver.patch

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    TI__Guru**** 433145 points

    Updated patch for the PSDKRA8.0 release. Apply attached patch on the folder ti-processor-sdk-rtos-j721e-evm-08_00_00_12\pdk_jacinto_08_00_00_37 and rebuild PDK, SDK and vision apps. 

    /cfs-file/__key/communityserver-discussions-components-files/791/5554.Added_5F00_Support_5F00_For_5F00_lane_5F00_speed_5F00_in_5F00_DSI_5F00_Driver.patch

    Regards,

    Brijesh