[FAQ] SK-TDA4VM: Can somebody provide the PCB schematics and layout from sprr438 in Altium format?

Pedantus

Part Number: SK-TDA4VM

Hi,

We would like to use the SK-TDA4VM PCB schematics and layout as a starting point for our own PCB design. Especially the DDR4 high-speed design and the PMIC design would save us a lot of design time and risk. Unfortunately we have Altium but the delivered design files in sprr438.zip are made with ?cadence? Altium are not able to import these files without an installed cadence software.

Can somebody convert the design files to the Altium format and provide the converted files? The dream would be that this “somebody” could check the plausibility of the generated files.
(My fear is, if I try to convert the files with semiofficial tools, the result is not accurate. For instance, the impedance could be inaccurate.)

Many thanks in advance!

over 2 years ago

0 Robert Eschler over 2 years ago

TI__Mastermind 42680 points

I have tried importing the Allegro file into Altium, but am getting an extracta time-out error. I can run the extracta on the Allegro file if you can provide the specific command-line parameters needed for Altium.

0 Pedantus over 2 years ago in reply to Robert Eschler

Prodigy 130 points

I tried to find something in that direction from Altium and found the two files I have attached:
Allegro2Altium.bat (I have renamed it to .txt, otherwise I could not attach it.)
AllegroExportViews.txt.

The description of the import process in Altium is here:
https://www.altium.com/documentation/altium-designer/allegro-import-ad
but I do not have an installed cadence on my PC.

Does that help?

AllegroExportViews.txt

# Start of Allegro to Altium Designer Board View
BOARD
    BOARD_NAME
    BOARD_UNITS
    BOARD_EXTENTS_X1
    BOARD_EXTENTS_Y1
    BOARD_EXTENTS_X2
    BOARD_EXTENTS_Y2
    BOARD_THICKNESS
END
# End of Allegro to Altium Designer Board View

# Start of Allegro to Altium Designer Layer View
LAYER
    LAYER_SORT
    LAYER_SUBCLASS
    LAYER_ARTWORK
    LAYER_USE
    LAYER_CONDUCTOR
    LAYER_DIELECTRIC_CONSTANT
    LAYER_ELECTRICAL_CONDUCTIVITY
    LAYER_MATERIAL
    LAYER_THERMAL_CONDUCTIVITY
    LAYER_THICKNESS
END
# End of Allegro to Altium Designer Layer View

#
# Connectivity - Simple Net list.
#
CONNECTIVITY
  NET_NAME != ''
  CLASS = 'PIN'
  NET_NAME_SORT
  NODE_SORT
  NET_NAME
  REFDES
  PIN_NUMBER
  PIN_NAME
  SUBCLASS
END

#
# Net Rules View
#
NET
  NET_NAME_SORT
  NET_NAME
  NET_STATUS
  NET_CAPACITANCE
  NET_ETCH_LENGTH
  NET_ETCH_WIDTH_AVERAGE
  NET_IMPEDANCE_AVERAGE
  NET_IMPEDANCE_MAXIMUM
  NET_IMPEDANCE_MINIMUM
  NET_INDUCTANCE
  NET_MANHATTAN_LENGTH
  NET_MANHATTEN_LENGTH
  NET_PATH_LENGTH
  NET_PROPAGATION_DELAY
  NET_RESISTANCE
  NET_VIA_COUNT
  NET_BUS_NAME
  NET_PHYSICAL_TYPE
  NET_PROPAGATION_DELAY
  NET_DIFFERENTIAL_PAIR
  NET_DRIVER_TERM_VAL
  NET_ECL
  NET_ECL_TEMP
  NET_FIXED
  NET_LOAD_TERM_VAL
  NET_RELATIVE_PROPAGATION_DELAY
  
  NET_MAX_BVIA_STAGGER
  NET_MAX_FINAL_SETTLE
  NET_MAX_OVERSHOOT
  NET_MAX_PARALLEL
  
  NET_MAX_VIA_COUNT
  NET_MIN_BVIA_GAP
  NET_MIN_BVIA_STAGGER
  NET_MIN_LINE_WIDTH
  NET_MIN_NOISE_MARGIN
  NET_NET_PHYSICAL_TYPE
  NET_NET_SPACING_TYPE
  NET_NO_GLOSS
  NET_NO_PIN_ESCAPE
  NET_NO_RAT
  NET_NO_RIPUP
  NET_NO_ROUTE
  NET_NO_TEST
  NET_PROBE_NUMBER
  NET_RATSNEST_SCHEDULE
  NET_ROUTE_PRIORITY
  NET_ROUTE_TO_SHAPE
  NET_SAME_NET
  NET_SPACING_TYPE
  NET_STUB_LENGTH
  NET_TS_ALLOWED
  NET_VIA_LIST
  NET_VOLTAGE
  NET_WEIGHT

END

#
# Pad Stack View
#
PAD_DEF
END

#
# Board geometries minus symbols.
#
FULL_GEOMETRY

  CLASS != 'PACKAGE GEOMETRY'
  CLASS
  SUBCLASS
  SYM_TYPE != 'PACKAGE'
  RECORD_TAG
  GRAPHIC_DATA_NAME
  GRAPHIC_DATA_NUMBER
  GRAPHIC_DATA_1
  GRAPHIC_DATA_2
  GRAPHIC_DATA_3
  GRAPHIC_DATA_4
  GRAPHIC_DATA_5
  GRAPHIC_DATA_6
  GRAPHIC_DATA_7
  GRAPHIC_DATA_8
  GRAPHIC_DATA_9
  GRAPHIC_DATA_10
  PIN_NUMBER
  PAD_STACK_NAME
  PAD_SHAPE_NAME
  PAD_TYPE
  PAD_FLASH
  DRILL_HOLE_X
  DRILL_HOLE_Y
  NET_NAME
  PIN_X
  PIN_Y
  VIA_X
  VIA_Y

END

#
# Extract footprint (symbol) geometries 
#
FULL_GEOMETRY


  SYM_NAME
  SYM_NAME != ''
  SYM_TYPE
  COMP_DEVICE_TYPE

  REFDES

  CLASS
  SUBCLASS
  RECORD_TAG
  GRAPHIC_DATA_NAME
  GRAPHIC_DATA_NUMBER
  GRAPHIC_DATA_1
  GRAPHIC_DATA_2
  GRAPHIC_DATA_3
  GRAPHIC_DATA_4
  GRAPHIC_DATA_5
  GRAPHIC_DATA_6
  GRAPHIC_DATA_7
  GRAPHIC_DATA_8
  GRAPHIC_DATA_9
  GRAPHIC_DATA_10
  PIN_NUMBER
  PIN_NAME
  PIN_TYPE
  PAD_STACK_NAME
  PAD_SHAPE_NAME
  PAD_TYPE
  PAD_FLASH
  DRILL_HOLE_X
  DRILL_HOLE_Y
  NET_NAME
  PIN_X
  PIN_Y

END

#
# Symbol Instances.
#
SYMBOL
     SYM_TYPE
     SYM_NAME
     REFDES
     SYM_MIRROR
     SYM_ROTATE
     SYM_X
     SYM_Y
     SYM_CENTER_X
     SYM_CENTER_Y
     SYM_LIBRARY_PATH
END

Allegro2Altium.txt

extracta.exe %1 AllegroExportViews.txt AllegroBoard.txt AllegroLayer.txt AllegroConnectivity.txt AllegroNetRules.txt AllegroPadStack.txt AllegroGeometry.txt AllegroSymbolDefinitions.txt AllegroSymbolInstances.txt AllegroAddlGeometry.txt AllegroMultiStackup.txt
COPY AllegroBoard.txt+AllegroLayer.txt+AllegroConnectivity.txt+AllegroNetRules.txt+AllegroPadStack.txt+AllegroGeometry.txt+AllegroSymbolDefinitions.txt+AllegroSymbolInstances.txt+AllegroAddlGeometry.txt+AllegroMultiStackup.txt AllegroASCII.txt
DEL AllegroBoard.txt AllegroLayer.txt AllegroConnectivity.txt AllegroNetRules.txt AllegroPadStack.txt AllegroGeometry.txt AllegroSymbolDefinitions.txt AllegroSymbolInstances.txt AllegroAddlGeometry.txt AllegroMultiStackup.txt
MOVE /-Y AllegroASCII.txt %1.alg