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GPMC Burst using DMA

Midson
Intellectual 835 points
LA Capture 
Our Tests and LA Captures:

1) Image1: Frame-1, Burst Mode-16, Element Size-16, Elements-16 => 32 Bytes @ 1 Burst

2) Image2: Frame-1, Burst Mode-16, Element Size-32, Elements-16 => 64 Bytes @ 1 Burst
Data toggling 2 times within the WE.

3) Image3: Frame-1, Burst Mode-16, Element Size-32, Elements-32 =>128 Bytes @ 2 Bursts
Expected is 1 Burst with data toggling 4 times within the WE.

4) Image4: Frame-1, Burst Mode-16, Element Size-32, Elements-64 => 256 Bytes @ 4 Bursts
Expected is 1 Burst with data toggling 8 times with the WE.

a) Is it possible transmit more then 64 Bytes in a Single burst?
b) Is there any setting in DMA will help to achieve this?
DM37x TRM (11.4.5) say, DMA can do max of 64bytes in single burst? Why is this limitation? 
c) Is it our understanding is correct? 

Are we going in a right direction?

NOTE: 
We are NOT seeing any difference with ioremap, ioremap_cached, ioremap_nocache.
We are using the DMA API used in OneNAND Driver.
We are getting "DMA Transaction and DMA Alignment Errors".
Read is not yet tested.

Can someone throw more light on this?
  • 0
    TI__Guru*** 125430 points

    Midson said:
    a) Is it possible transmit more then 64 Bytes in a Single burst?

    No, 64 bytes is the largest in general.  For the GPMC the largest burst will be 32 bytes because that's the size of the FIFO in the GPMC.  This is documented in the GPMC Chapter in the section called "L3 Interconnect Interface".

  • 0 in reply to Brad Griffis
    Intellectual 835 points

    Thanks Brad. As of now, I am able to transmit 4 words with in a WE/OE using GPMC Burst (with-out DMA). Is it possible to mix the GPMC Burst and DMA  to transmit the same 64bytes in a less time?

    Kindly refer my other query also (http://e2e.ti.com/support/dsp/sitara_arm174_microprocessors/f/416/p/105253/374077.aspx#374077).

    * DMA Transaction and DMA Alignment Errors are fixed by proper memory handling and by using the 32 aligned address.

  • 0 in reply to Midson
    TI__Guru*** 125430 points

    Midson said:
    As of now, I am able to transmit 4 words with in a WE/OE using GPMC Burst (with-out DMA).

    What's a "word"?  Is that 4 16-bit GPMC transactions inside a single WE/OE?  I think the best you can possibly achieve is 16 16-bit  transfers on the GPMC due to the 32-byte FIFO size inside the GPMC.  In order to achieve this you would need to configure the DMA for 32-bit packed accesses with bursting.

  • 0 in reply to Brad Griffis
    Intellectual 835 points

    Thanks Brad. Word == 16bits and 4W transmitted in a single WE/OE. Currently the DMA is configured for 16x16.

    1. The test code is simple write followed by read. In this, the gap between write and read is 22us for 1 frame and 104us for 16 frames. Can you give some inside on why the gap increases with no of frames? Basically this increase is blocking purpose of achieving the more throughput.

    2. How to transmit the 16x16 with minimum no of cycle?

    3. Is it possible to mix both GPMC Burst and DMA to achieve the (2)?

    4. What do you mean by DMA Bursting? As of now, all my DMA Bursting are 16 single writes, which are following each other very closely. Is it the DMA Bursting?