FAQ Contents
There are a variety of NOR and NAND based flash parts available that can make choosing a flash memory for a design challenging; picking a flash to use for booting can be particularly challenging due to the lack of software control or flexibility compared to other use cases. This FAQ will show a rough decision guideline for how to choose a flash part including example links to documentation and how/when to use them. While this FAQ features AM64x/AM62x prominently, the same decision making flow applies to all K3 devices with the same OSPI IP.
Applicable Devices/Families
- AM64x
- AM62x
- AM65x
- AM243x
- TDA4x
- DRA8x
IP Limitations/Requirements
The OSPI controller is used across many Sitara and Jacinto devices and it's limitations are the first thing to examine when choosing a flash device. There are not many pertinent things to consider besides the following:
- Maximum dummy cycles is 31
There may be limitations that affect niche cases but for the majority of NOR/NAND flash the features available will be sufficient. For a full description of the OSPI IP(s) instantiated on a device, see the Peripherals section in the TRM (Technical Reference Manual) of the device chosen. (Ex: see section 12.4.2 in the AM62x TRM or section 12.3.2 in the AM64x/AM243x TRM). The OSPI section in a particular device's TRM will detail features and registers including any revisions that may be unique to a device.
Each product page has a list of technical documentation:
An example link to the AM62x TRM is shown below (please reference the product page for the latest TRM revision)
AM62x TRM (linked 10/30/22): https://www.ti.com/lit/pdf/spruiv7
Device Limitations/Requirements
The next level to consider are qualities specific to a device; each device has a datasheet showing various electrical characteristics including switching/timing characteristics and layout guidelines. For OSPI the board design/layout guidelines and timing/switching characteristics should be read and considered when planning the board topology and picking a flash device. While other combinations of clocking topologies/modes can be done, they are not officially supported unless in the datasheet. These guidelines also do not replace doing board level simulations and we recommend always performing them. We also recommend validating a flash part on an actual board before any mass production.
Another document to consult is the Device Errata sheet, which will contain usage notes and known bugs with the device. Taking AM64x for example: errata i2351 "OSPI: Controller does not support Continuous Read mode with NAND Flash" will affect choosing a NAND flash device to use while errata i2249 "OSPI: Internal PHY Loopback and Internal Pad Loopback clocking modes with DDR timing inoperable" will affect certain OSPI DDR mode configurations.
- OSPI/QSPI/SPI Board Design and Layout Guidelines
- Use this section to determine an appropriate clocking topology for connecting to the flash and planning the layout. The timing and switching characteristics information should be used in conjunction with this to determine which topology is best suited for a usecase.
- OSPI Timing and Switching Characteristics
- This section offers insight into max frequencies and electrical characteristics in the various modes the OSPI controller can operate in. Use in conjunction with the design and layout guidelines.
- Device Errata for usage notes and known bugs
- This document will note any usage notes to be aware of and bugs known with the OSPI IP, implementation, or OSPI boot.
The device datasheet can be found in the product page under technical documentation, an example link to the AM64x datasheet is shown below (please reference the product page for the latest datasheet revision)
AM64x Datasheet (linked 10/30/22): https://www.ti.com/lit/gpn/am625
Errata can be found in the technical documentation section of a product, an example link to the AM64x errata is shown below (please reference the product page for the latest errata revision)
AM64x errata (linked 10/30/22): https://www.ti.com/lit/er/sprz457f/sprz457f.pdf
Use-case Limitations/Requirements
The final set of restrictions will depend on the usecase that OSPI will be used in, the most popular ones are below. At this point these usecases will determine the final functional limits/requirements, but the the IP limits/requirements and Device Limits/Requirements are still a pre-requisite for any of these usecases on a given device.
Boot
By far the most popular, this use case involves loading an non-volatile image to flash that the ROM code (on power-on) will then load into system memory. Once loaded the Secondary Bootloader will proceed with the rest of system initialization and do any additional configuration of the chip and possibly the OSPI IP. The important set of requirements/limitations is what the ROM will do and is capable of since it cannot be changed by any application. For all details related to boot see the appropriate section in the TRM for a given device ( Section 4.4.1 OSPI, xSPI, QSPI, SPI Boot in the AM64x TRM for example).
Linux
Linux is a high level operating system suited for embedded enivronments. We have a Linux SDK provided, for links to download and the most current documentation see the Download Options under Software Development in the product page.
SDK Linux OSPI documentation (linked 10/30/22): https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/08_04_01_04/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/QSPI.html
RTOS/Bare-metal/Other
For all RTOS or bare-metal type applications, see the MCU+ SDK for software resources. The MCU+ SDK documentation details what is provided/required. Example links is given below, for the most current documentation see the Download Options under Software Development in the product page.
(Linked 10/30/22)
U-boot
U-boot is a popular open source bootloader that acts as the secondary bootloader in our devices. To understand what the U-Boot software we provide requires for using OSPI, see the U-boot section in SDK Linux documentation. An example link is given below, for the most current documentation see the Download Options under Software Development in the product page.
Linux U-boot OSPI/QSPI (linked 10/30/22): https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/08_04_01_04/exports/docs/linux/Foundational_Components/U-Boot/UG-QSPI.html
XIP
This use case (short for eXecute-In-Place) involves a core directly executing code from the flash instead of first loading into internal memory. There aren't many restrictions in this usecase since this will likely happen in a custom application. Depending on the software environment you may need to write/add in custom code to configure the flash for XIP and configure any core's MMU/MPU to have the OSPI memory region as executable (and recommend cacheable as well for applicable cores, this will increase performance and allow cache-line fetches).
Storage
This use case involves using the OSPI IP to write/read data to a flash memory for non-volatile storage. There aren't many restrictions in this use-case since this will likely happen in a custom application. Depending on the software environment you may need to write/add in custom code to configure/talk to a flash device and pick an appropriately sized flash to store all the information necessary.
(WIP) Non-exhaustive examples on how to use the FAQ for Boot for AM62x
Using OSPI as a boot method is not only the most popular usecase for using OSPI but also the most restrictive since there is relatively little control over what the ROM code does, here are some examples to determine if they'll work with a device's boot or not. This is a non-exhaustive list using AM62x as a reference and is not meant to be comprehensive.
Starting with the first thing to consider, IP limitations: any flash device will need to use 31 dummy cycles for any applicable commands. This often comes into play at higher speeds, so while taking a note of this it should not come into play. When it comes to the device limitations/requirements, the choice of clocking topology can be influenced by board resources (space/cost/pins) and the flash itself. For the purposes of these examples, we will assume that the board level simulations we recommend performing have resulted in a compatible board topology that passes simulations.
The errata for a specific device will come in handy to determine any OSPI or Boot specific usage notes and advisories. Looking at the AM62x errata (as of 12/16/22), there are the following:
- Usage Note i2351 — OSPI: Controller does not support Continuous Read mode with NAND Flash
- Advisory i2307 — Boot: ROM does not properly select OSPI clocking modes based on BOOTMODE
- Advisory i2189 — OSPI: Controller PHY Tuning Algorithm YES
- Advisory i2249 — OSPI: Internal PHY Loopback and Internal Pad Loopback clocking modes with DDR timing inoperable
Reviewing these, we can keep the following things in mind when picking a flash device:
- NAND flash devices offering a continuous read mode must have that mode disabled, otherwise it cannot be used in boot
All other advisories pertain to OSPI clocking topology or OPSI operation outside of boot.
MT35XU512ABA (NOR Flash)
Being a NOR flash device, we can rule out Serial NAND boot. That leaves the xSPI, OSPI, QSPI, SPI boot modes to consider.
- For xSPI boot, this memory offers a read command of 0x0B in 1S-1S-1S mode with 3 address bytes and 8 dummy cycles. In 8D-8D-8D mode the read command takes 16 dummy cycles and 4 address bytes. xSPI boot can use either of these formats for that command, which means this should be compatible with xSPI boot.
- For OSPI boot, this memory offers the required read command of 0x8B in 1S-1S-8S mode with 3 address bytes and 8 dummy cycles, meaning this memory should be compatible with OSPI boot.
- For QSPI boot, this memory does not offer a quad read command and is therefore not compatible with QSPI boot.
- For SPI boot, this memory offers the required read command of 0x03 with 3 address bytes and 0 dummy cycles, meaning this memory should be compatible with SPI boot.
Another note to examine is that in the command table some of these commands have a configurable number of dummy cycles via a register in the flash; this should be set to align with the desired bootmode.
MT25Q (NOR Flash)
Being a NOR flash device, we can rule out Serial NAND boot. That leaves the xSPI, OSPI, QSPI, SPI boot modes to consider. Since this device is a QSPI device, we can rule out xSPI and OSPI.
- For QSPI boot, this memory offers the required read command of 0x6B in 1S-1S-4S mode with 3 address bytes and 8 dummy cycles, meaning this memory should be compatible with QSPI boot.
- For SPI boot, this memory offers the required read command of 0x03 with 3 address bytes and 0 dummy cycles, meaning this memory should be compatible with SPI boot.
Another note to examine is that in the command table some of these commands have a configurable number of dummy cycles via a register in the flash; this should be set to align with the desired bootmode.
S25HS02GT, S25HS04GT (NOR Flash)
Being a NOR flash device, we can rule out Serial NAND boot. That leaves the xSPI, OSPI, QSPI, SPI boot modes to consider. Since this device is a QSPI device, we can rule out xSPI and OSPI.
- For QSPI boot, this memory offers the required read command of 0x6B in 1S-1S-4S mode with 3 address bytes and 8 dummy cycles, meaning this memory should be compatible with QSPI boot.
- For SPI boot, this memory offers the required read command of 0x03 with 3 address bytes and 0 dummy cycles, meaning this memory should be compatible with SPI boot.
Another note to examine is that in the command table some of these commands have a configurable number of dummy cycles via a register in the flash; this should be set to align with the desired bootmode.
Additional Reference