Regarding EDMA3 interrupt generation using dispatcher

Bharti,

I assume you are planning to generate the EDMA3 TPCC2 global transfer completion interrupt (system interrupt 22 of CP-INTC0) in CorePac0 (host interrupt 40, INTC0_OUT(32+8+11*n), n=0 for CorePac0). Please correct me if I am wrong.

1. Please check if the actual TPCC2 transfer has been completed (the corresponding bits in IPR/IPRH will be set, please refer to EDMA3 user's guide for details).

2. Only the code of CP-INTC enabling has been showed above, which seems fine. But we also need to enable the interrupt controller in CorePac, which is related to the ISR hook up as well. The example code of CorePac INTC enabling and the modified CP-INTC enabling are attached at the end. Please let us know if you have any questions.

Sincerely,

Steven

PLT_cpintc_config()

{

            CSL_CPINTC_Handle       hnd;

            /* Program CPINTC */

            /* Open the handle to the CPINT Instance (edma3 events are mapped to CPINTC0)*/

            hnd = CSL_CPINTC_open (CSL_CP_INTC_0);

            if (hnd == 0)

            {

                        System_printf ("PLT_cpintc_config : Unable to open CPINTC_0\n");

                        return -1;

            }

            /* Disable all host interrupts. */

            CSL_CPINTC_disableAllHostInterrupt(hnd);

           /* Configure no nesting support in the CPINTC Module. */

           CSL_CPINTC_setNestingMode (hnd, CPINTC_NO_NESTING);

             /* Map System Interrupt 22 to channel 40 */

            CSL_CPINTC_mapSystemIntrToChannel (hnd, 22, 40);

            /* Map Channel 40 to Host Interrupt 40 */

            /* Host interrupt mapping is fixed */

            //CSL_CPINTC_mapChannelToHostInterrupt (hnd, 40, 40);

            /* Enable system interrupt 22 */

            CSL_CPINTC_enableSysInterrupt (hnd, 22);

            /* Enable host interrupts. */

            CSL_CPINTC_enableHostInterrupt (hnd, 40);

            /* Enable all host interrupts also. */

            CSL_CPINTC_enableAllHostInterrupt(hnd);

            return;

}

static void test_isr_handler (void* handle)

{

            /* EDMA3 Event Handler ISR */

           /* “PLT_Edma3EventHook(CSL_TPCC2_INTC1_OUT24, tcc37Fxn) may be added here */

}

void main (void)

{

    /* CorePac(GEM) INTC module initialization */

    intcContext.eventhandlerRecord = EventHandler;

    intcContext.numEvtEntries      = 10;

    if (CSL_intcInit(&intcContext) != CSL_SOK)

    {

        printf("Error: GEM-INTC initialization failed\n");

        return;

    }   

    /* Enable NMIs */

    if (CSL_intcGlobalNmiEnable() != CSL_SOK)

    {

        printf("Error: GEM-INTC global NMI enable failed\n");

        return;

    }

    /* Enable global interrupts */

    if (CSL_intcGlobalEnable(&state) != CSL_SOK)

    {

        printf ("Error: GEM-INTC global enable failed\n");

        return;

    }

    /* Open the INTC Module for Vector ID: 4 and Event ID: 29 (C6678) */

    /* Refer to the interrupt architecture and mapping document for the Event ID  (INTC0_OUT(32+8+11*n))*/

    vectId = CSL_INTC_VECTID_4;

    hTest = CSL_intcOpen (&intcObj, 29, &vectId , NULL);

    if (hTest == NULL)

    {

        printf("Error: GEM-INTC Open failed\n");

        return;

    }

    /* Register an call-back handler which is invoked when the event occurs. */

    EventRecord.handler = &test_isr_handler;

    EventRecord.arg = 0;

    if (CSL_intcPlugEventHandler(hTest,&EventRecord) != CSL_SOK)

    {

        printf("Error: GEM-INTC Plug event handler failed\n");

        return;

    }

    /* Enabling the events. */

    if (CSL_intcHwControl(hTest,CSL_INTC_CMD_EVTENABLE, NULL) != CSL_SOK)

    {

        printf("Error: GEM-INTC CSL_INTC_CMD_EVTENABLE command failed\n");

        return;

    }

     printf ("Debug: GEM-INTC Configuration Completed\n");

     /* Initialize the CP-INTC configuration */

     PLT_cpintc_config();

     /* Configure the EDMA3 and start the transfer */

    ............  

}

Thanks Steven,

With INTC & CPINTC modules,I had generated the interrupt with EDMA3 for channel no 2 (event id 58),now this edma3 channel no. is same as INTC channel no.If I change the EDMA3 channel No. so that the scinario is such that any of the edma3 channels can  create a unique interrupt  of the same event id i.e 58 and system interrupt no. 22.,the interrupt is not generated.

So my question is : Is it mandatory that INTC channel number & edma channel no. should be same ?

Can I generate a unique interrupt from multiple edma channels(using ORing logic) i.e N:I mapping ?

Bharti,

EDMA3 module allows multiple channels triggering the same interrupt to cause a DSP to execute the same ISR for different channels.

1. There are 3 EDMA3 channel controller (CC) instances in C667x device, EDMA3_CC0,1,2. Each EDMA3_CC can generate a single completion interrupt for the global region on behalf of all DMA/QDMA channels. We take EDMA3_CC2 as an example, the global transfer completion interrupt is EDMA3_CC2_GINT. When you setup the EDMA parameter set, you can choose to use the global region. And the transfer completion code (TCC) can be programmed to any value for a DMA/QDMA channel. That means multiple channels can use the same TCC value to generate the EDMA3_CC2_GINT interrupt to DSP to execute the same ISR. Please refer to section 2.9 in EDMA3 user's guide for details.

2. We take C6678 as an example. The EDMA3_CC2_GINT is the input event #22 (fixed) of chip-level interrupt controller 0&1 (chip-level INTC0 is for CorePac0~3 and chip-level INTC1 is for CorePac4~7). If you want to generate an interrupt to CorePac0, you can enable chip-level INTC0 only.

There are 160 inputs for chip-level INTC0 but only about 25 outputs from chip-level INTC0 to CorePac0. In your program, you can map the input event #22 to any chip-level INTC0 outputs, which are the system event input of CorePac0 INTC. In our previous example, we map the chip-level INTC0 input #22 to output #40, which is the input #29 (INTC0_OUT(32+8)) of CorePac0 INTC. But you can map the EDMA3_CC2_GINT to other output of chip-level INTC0 and find the corresponding input number for CorePac INTC.

Please refer to C6678 data manual and chip-level INTC user's guide for details.

3. Then we need to enable the interrupt on CorePac0 INTC. There are 128 input events for each CorePac, including input event #29 (now is the allocated for EDMA3_CC2_GINT). But there are only 12 maskable interrupt (DSPINT4~15) available. We can choose to map the input #29 to any vector #4~15. And we choose vector #4 in our previous example. Please refer to CorePac user's guide for details.

After programming EDMA3, enabling chip-level INTC0 and CorePac0 INTC, we are now able to generate the unique global completion interrupt from any EDMA channels to the CorePac. And the channel or event number is controllable on all EDMA3, chip-level INTC and CorePac level INTC.

Hope it helps.

Sincerely,

Steven