AM3874 GPMC_WAIT and burst access

Hi,

I got some my questions relative these questions as the following.

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/187772.aspx

And I think the answer of these questions. Please see the below. And check my answers.

Q1) I was advised that there is no specific timing between GPMC_WAIT deassersion and assertion again in before question. Is this meaning that next GPMC_WAIT signal can assert  as soon as the previous GPMC_WAIT is recoginzed? Of course it assumes WAITMONITERINGTIME is kept.

--->  My answer is yes. GPMC_WAIT can deassert/assert after the previous GPMC_WAIT is recoginzed once.

Q2) According to the FIG.11-8 of TRM, WAIT signal only needs to satisfy WAITMONITERINGTIME for  D0. D1, D2 and D3 doesn't need to satisfy it, do it?

---> For Burst read, it is needed just only one Wait signal assertion. 

However , I have new question. Please see the below. Is this way(WAIT signal assertion/deassertion) possible?

Q3) I was advised WAIT signal toggle in WAIT inactive period is not effect, but it is not recommended.  According to the additional information, customer would like to use one WAIT pin for multiple CS(Customer would like to use both Asynchronous I/F and Synchronous I/F each CS(Chip Select) with one WAIT pin). Can TI guarantee the GPMC of AM3874 with this use?

---> It is not guranteed because critical situation of GPMC internal.

Q4)  According to the data sheet(Fig 8-21 to Fig. 8-26),  the assertion of GPMC_WAIT signal is doen when GPMC_ADV_ALE signal is low. Is there any timing requirement between GPMC_WAIT and GPMC_ADV_ALE?

---> It is no relationship between GPMC_WAIT and GPMC_ADV_ALE. Both signal is independent..

Q5) Multiple(Burst)  and Singl access is configured each CS(chip select) on GPMC register . If Burst (multiple access if synchronous) is set,  it is occurred only burst cycle,  single cycle never occurred. The burst length must be set in GPMC register. Which does this length represent variable length or fixed length?

---> If burst is set, it is occurred only burst cycle. It is never happened single cycle when burst mode is set in GPMC register.

Please let me know , "Which does this rength for setting in GPMC register represent variable length or fixed length?

Please give me your advices.

Best regards,

Michi

Hello Michi-san,

>> Q1) I was advised that there is no specific timing between GPMC_WAIT deassersion and assertion again in before question. Is this meaning that next GPMC_WAIT signal >> can assert  as soon as the previous GPMC_WAIT is recoginzed? Of course it assumes WAITMONITERINGTIME is kept.

>> --->  My answer is yes. GPMC_WAIT can deassert/assert after the previous GPMC_WAIT is recoginzed once.

Chaitanya :: Yes. this is correct.

>> Q2) According to the FIG.11-8 of TRM, WAIT signal only needs to satisfy WAITMONITERINGTIME for  D0. D1, D2 and D3 doesn't need to satisfy it, do it?

>> ---> For Burst read, it is needed just only one Wait signal assertion. 

>> However , I have new question. Please see the below. Is this way(WAIT signal assertion/deassertion) possible?

Chaitanya: If it toggles the way you have shown in the image, then for each D1,D2,D3 also need to satisfy WAITMONITERINGTIME.

>> Q3) I was advised WAIT signal toggle in WAIT inactive period is not effect, but it is not recommended. 

---> It is not guranteed because critical situation of GPMC internal.

Correct. Agreed.

>>According to the additional information, customer would like to use one WAIT pin for multiple CS(Customer would like to use both Asynchronous I/F and Synchronous I/F each CS(Chip Select) with one WAIT pin). Can TI guarantee the GPMC of AM3874 with this use?

Chaitanya: This is possible , but not advised. GPMC has 4 wait pins, Is the customer using all of them? Can you advice him to use another Wait pin that is not used?

Best regards,

Chaitanya

Dear Chaitanya-san,

Thank you for your reply.

> Q5) Multiple(Burst)  and Singl access is configured each CS(chip select) on GPMC register . If Burst (multiple access if synchronous) is set,  it is occurred only burst

> cycle,  single cycle never occurred. The burst length must be set in GPMC register. Which does this length represent variable length or fixed length?

> ---> If burst is set, it is occurred only burst cycle. It is never happened single cycle when burst mode is set in GPMC register.

> Please let me know , "Which does this rength for setting in GPMC register represent variable length or fixed length?

Coluld you give me your answer for the above burst length question(blue color sentence)?

> >>According to the additional information, customer would like to use one WAIT pin for multiple CS(Customer would like to use both Asynchronous I/F and

> Synchronous I/F each CS(Chip Select) with one WAIT pin). Can TI guarantee the GPMC of AM3874 with this use?

> Chaitanya: This is possible , but not advised. GPMC has 4 wait pins, Is the customer using all of them? Can you advice him to use another Wait pin that is not used?

--> Probably customer thinks to connect except memory to GPMC, such asic, some sub MCU, and so on. So its external device can have both I/F asynchronous and synchronous in a device. So customer asks such question to us. In such condition, can GPMC's CS work correctly?

Best regards,
Michi

Hello Michi-san,

> Please let me know , "Which does this rength for setting in GPMC register represent variable length or fixed length?

Chaitanya: Not sure if I got your question correctly. If your Question is: How to program the MaxburstLength in case of Multiple(Burst) access.

Please use GPMC_CONFIGX_2[24:23] = ATTACHEDDEVICEPAGELENGTH. This will give you MaxBurstLength=4,8,16

--> Probably customer thinks to connect except memory to GPMC, such asic, some sub MCU, and so on. So its external device can have both I/F asynchronous and synchronous in a device. So customer asks such question to us. In such condition, can GPMC's CS work correctly?

Chaitanya : Need some time for this. Need to check the design and get back.

Best regards,

Chaitanya

Dear Chaitanya-san,

Thank you for your answer.

>> Please let me know , "Which does this rength for setting in GPMC register represent variable length or fixed length?

>Chaitanya: Not sure if I got your question correctly. If your Question is: How to program the MaxburstLength in case of Multiple(Burst) access.

>Please use GPMC_CONFIGX_2[24:23] = ATTACHEDDEVICEPAGELENGTH. This will give you MaxBurstLength=4,8,16

Sorry for your confusion. I would like to know whether GPMC burst transfer supports variable-length burst like as DDR memory.

But I think, in TRM, there is not shown the phase of sending burst length in same cycle. So GPMC's burst transfer is fixed -length burst only.

Is my understanding right?

Best regards,

Michi

Hi, Chaitanya-san,

Thank you for your support.

I have one more question from my customer.

Regarding Q3)

>>According to the additional information, customer would like to use one WAIT pin for multiple CS(Customer would like to use both Asynchronous I/F and Synchronous I/F each CS(Chip Select) with one WAIT pin). Can TI guarantee the GPMC of AM3874 with this use?

> Chaitanya: This is possible , but not advised. GPMC has 4 wait pins, Is the customer using all of them? Can you advice him to use another Wait pin that is not used?

Please confirm me you said. According to my understanding, GPMC has 2 wait pins(WAIT0, WAIT1 only), not 4 wait pins. Is my understanding right?

Then,  customer said to me.  When synchronous I/F using,  WAIT1 must select the clock. So they only use WAIT0. This means that WAIT pin is only one for CS0-CS4.

Is our understanding wrong?

Please let me know.

Best reagrds,

Michi

Michi-san,

>>Please confirm me you said. According to my understanding, GPMC has 2 wait pins(WAIT0, WAIT1 only), not 4 wait pins. Is my understanding right?

My mistake. The GPMC module has capacity to support 4 wait pins but in AM3874 only 2 wait pins WAIT0, WAIT1 are brought out onto pin level.

>>Then,  customer said to me.  When synchronous I/F using,  WAIT1 must select the clock. So they only use WAIT0. This means that WAIT pin is only one for CS0-CS4.

This question needs some SOC/pin-connection level expert to answer.  Normally WAIT1, if brought out needs to work continuously from start of access to end of access.

So I think we need to confirm this from a SOC/integration/pin-connection expert.

As for using the same wait pin, we need some more time to check this.

Best regards,

Chaitanya

Dear Chaitanya-san,

Thank you for your quick reply.

>This question needs some SOC/pin-connection level expert to answer.  Normally WAIT1, if brought out needs to work continuously from start of access to end of access.

>So I think we need to confirm this from a SOC/integration/pin-connection expert.

>As for using the same wait pin, we need some more time to check this.

Could you confirm this matter to SOC/Integration/pin-connection exprt in your side?

I appreciate your support.

Best regards,

Michi