AM335x USBn Core Registers

Joe Schirmer

The TRM does not describe the USBn Core registers (base address 0x4740_1400 for USB0 and 0x4740_1C00 for USB1).

Also, while I'm asking questions, TRM section 16.3.4 "Clock, PLL, and PHY Initialization" is referring to reserved address, not to any particular Registers that I can identify. Is there a more accurate description of what must be done to initialize the USBs' Clock, PLL, and PHY?

over 13 years ago

0 Biser Gatchev-XID over 13 years ago

TI__Guru**** 393215 points

Hi Joe,

There are some IP's (modules) used in the processor, which are licenced under certain legal conditions. For most of these NDA's apply. If you need additional information please cotact your TI FAE or representative.

Best Regards

Biser

0 Joe Schirmer over 13 years ago in reply to Biser Gatchev-XID

Prodigy 81 points

What about section 16.3.4 in the TRM? Are those values also covered under DNA or can you give a little more information on that?

0 Biser Gatchev-XID over 13 years ago in reply to Joe Schirmer

TI__Guru**** 393215 points

Since there is nothing more in the TRM, I think that this is the case. It does say in TRM section 16.1 that "Each USB controller is built around the Mentor USB OTG controller (musbmhdrc) and TI PHY."

Best Regards

Biser

0 Joe Schirmer over 13 years ago in reply to Biser Gatchev-XID

Prodigy 81 points

1.   Is the setup code shown in section 16.3.4 in the TRM correct?
1.a   If so, then why isn't the register memory mapped in Table 2-3 (L4_PER Peripheral Memory Map)?
1.b   If not, then what is the correct setup code/procedure?

0 -DK- over 13 years ago in reply to Joe Schirmer

TI__Mastermind 27890 points

As Biser pointed out, the USB IP used for this device is protected by NDA. The expectation is that customers wishing to write their own device driver (or modify a provided driver) would sign an NDA for full access to the relevant IP specification.

That said, we are in the process of reviewing an update to this section of the TRM that we hope will find a balance between providing our customers the information they need and protecting the IP of our provider. We do not have a schedule for completion as of yet so if you need access to more information than the TRM currently provides now, you will need to sign an NDA. If this is your wish, let me know and I can help you get the process started.

0 Joe Schirmer over 13 years ago in reply to -DK-

Prodigy 81 points

Do I need to sign a NDA in order to find out if section 16.3.4 in the TRM is correct? (See my three questions above)

0 -DK- over 13 years ago in reply to Joe Schirmer

TI__Mastermind 27890 points

Hi Joe,

No, the referenced addresses in the code example are not correct for AM335x.

0 Joe Schirmer over 13 years ago in reply to -DK-

Prodigy 81 points

Then onward to question 1b: "What is the correct setup code/procedure?" (Assuming that doesn't need a NDA)

0 Joe Schirmer over 13 years ago in reply to Joe Schirmer

Prodigy 81 points

I have signed the NDA and now have a copy of the the Mentor Graphics MISHMHDRC "ULPI Link Wrapper" and "Product Specification and Programming Guide" documents. But I still need am335x specific information such as the register offsets of the Mentor Core USB registers and the corrected am335x TRM section 16.3.4 describing the Clock, PLL and PHY setup.

Could you forward/supply that information?

Processors

Processors forum

AM335x USBn Core Registers