DM8148 Query

Hi Shakti,

Shakti Maan said:

general purpose register

Do you mean General Purpose Memory Controller (GPMC) registers, or General Purpose Input Output (GPIO) registers, or else?

Regards,
Pavel

HI

Like in atmel : GPBR (general purpose backup register) is given to store the variable which retains its value even after boot.

Am interested to know about this kinda of register : in short : i want to store my bootcount each time the system boot.

Regards

Smaan

Shakti,

You can use the RTC scratchpad registers: RTC_SCRATCH0_REG (at address 0x480C0060), RTC_SCRATCH1_REG (at address 0x480C0064) and RTC_SCRATCH2_REG (at address 0x480C0068).

From DM814x TRM:

chapter 20 Real-Time Clock (RTC)

20.2.5 Scratch Registers

The RTC provides three general-purpose registers (SCRATCHx_REG) that can be used to store 32-bit words -- these registers have no functional purpose for the RTC. Software using the RTC may find the SCRATCHx registers to be useful in indicating RTC states. For example, the SCRATCHx_REG registers may be used to indicate write-protection lock status or unintentional power downs. To indicate write- protection, the software should write a unique value to one of the SCRATCHx_REG registers when write-protection is disabled and another unique value when write-protection is enabled again. In this way, the lock-status of the registers can be determined quickly by reading the SCRATCH register. To indicate unintentional power downs, the software should write a unique value to one of the SCRATCHx_REG registers when RTC is configured and enabled. If the RTC is unintentionally powered down, the value written to the SCRATCH register is cleared. For more information, see the registers section.

When I set the values of 0x1 in RTC_SCRATCH0_REG in user space (with devmem2 tool), then I reboot and the value of 0x1 is still there, when I check it again.

root@dm814x-evm:~# devmem2 0x480C0060 w 0x1

root@dm814x-evm:~# reboot

......

root@dm814x-evm:~# devmem2 0x480C0060
/dev/mem opened.
Memory mapped at address 0x40302000.
Read at address  0x480C0060 (0x40302060): 0x00000001

But this is working after I modified a little the default linux kernel source code available in DM814x EZSDK 5.05.02.00

ti-ezsdk_dm814x-evm_5_05_02_00/board-support/linux-2.6.37-psp04.04.00.01/arch/arm/mach-omap2/devices.c

#define KICK0_REG    0x6c
#define KICK1_REG    0x70
#define OSC_REG        0x54

#define KICK0_REG_VAL    0x83e70b13
#define KICK1_REG_VAL    0x95a4f1e0
#define RESET_VAL    BIT(5)

static int ti81xx_rtc_init(void)
{
    void __iomem *base;
    struct clk *clk;

    clk = clk_get(NULL, "rtc_c32k_fck");
    if (!clk) {
        pr_err("rtc : Failed to get RTC clock\n");
        return -1;
    }

    if (clk_enable(clk)) {
        pr_err("rtc: Clock Enable Failed\n");
        return -1;
    }

    base = ioremap(TI81XX_RTC_BASE, SZ_4K);

    if (WARN_ON(!base))
        return -ENOMEM;

    /* Unlock the rtc's registers */
    __raw_writel(KICK0_REG_VAL, base + KICK0_REG);
    __raw_writel(KICK1_REG_VAL, base + KICK1_REG);

    /* Reset the RTC */
    //__raw_writel(RESET_VAL, base + OSC_REG);
    
    /*
     * After setting the SW_RESET bit, RTC registers must not be accessed
     * for 3 32kHz clock cycles (roughly 2200 OCP cycles).
     */
    udelay(100);

    /*
     * Unlock the rtc's registers again as the registers would have been
     * locked due to reset
     */
    __raw_writel(KICK0_REG_VAL, base + KICK0_REG);
    __raw_writel(KICK1_REG_VAL, base + KICK1_REG);

    iounmap(base);

    return  platform_device_register(&ti81xx_rtc_device);
}

I have commented the __raw_writel(RESET_VAL, base + OSC_REG); line, as it is resetting all RTC registers values to 0x0, thus we lost the 0x1 value that we set before the reboot. You have to create new uImage and use it, instead of the default one.

Best regards,
Pavel