How to select gstreamer clock as master clock in 1588-PTP.(PTPdv2 deamon running in backend)

Hi Ashwath,

This is what I found regarding PTP-1588:

http://processors.wiki.ti.com/index.php/TI81XX_PSP_ETHERNET_Switch_User_Guide#IEEE_1588.2F802.1AS_PTP_Support

Have a look also in the below links, might be in help:

http://processors.wiki.ti.com/index.php/TI81XX_PSP_04.04.00.01_Release_Notes
ti814x: cpsw: PTP time syncronization not happening when connected to Port 2

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/204024.aspx

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/197494.aspx

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/118687.aspx

http://e2e.ti.com/support/embedded/linux/f/354/t/152874.aspx

http://e2e.ti.com/support/embedded/linux/f/354/t/159662.aspx

BR
Pavel

Hi Pavel,

Thanks for the quick reply. Let me go through the links shared by you.

Best Regards,

Ashwath

Hi Pavel,

Any Idea how to select gstreamer clock as default clock for the PTP.

Any suggestions would be appreciated.

Regards,

Ashwath

Ashwath,

I am not sure what do you mean by "gstreamer clock", could you provide more details? In the below wiki you can find all the clocks available in the DM814x device, is your "gstreamer clock" some of those?

http://processors.wiki.ti.com/index.php/TI81XX_PSP_PM_CLOCK_FRAMEWORK_User_Guide

<kernel_installation>/arch/arm/mach-omap2/clock814x_data.c

BR
Pavel

Hi Pavel,

Actually I am not sure what is the default clock used by gstreamer for streaming in video-pipeline in a typical display app.

Our intention was to record the time stamp of 1588 incoming packets used by the clock that one used by gstreamer pipeline.

I thought the clock used by gstreamer is default system clock. Weather this clock is same as CPSW hardware clock which is used by PTP.

Best Regards,

Ashwath

Ashwath,

We have some info in the DM814x TRM, section 2.3.2 Clock Structure:

A separate 250 MHz reference is used for EMAC RGMII mode, this comes from a mux which also feeds
the 1588 reference clock. This clock has multiple options (see SERDES and Ethernet clocking diagram),
but defaults to VIDEO0 PLL. Therefore to use reset isolation, the user must use VIDEO0 PLL at 250 MHz,
which is also a suitable for 1588 reference clock rate.

And section 2.3.6 SERDES and Ethernet Clock Structure:

Also, several clock sources are required for the 1588 reference clock (cpts_rft_clk), also shown in Figure 2-10.

This 1588 reference clock also feeds the RGMII 250 MHz reference clock in case of RGMII. To use reset isolation, the VIDEO0 PLL option must be used for this clock since the clock mux control is not reset-isolated and VIDEO0 is the default clock. Note that 250 MHz is also a suitable frequency for 1588 reference. Also note that the use of this clock also means that VIDEO0 cannot be set to 54 MHz to support AVDAC use, which is a use case limitation. To use AVDAC, lose the reset isolation feature and select another clock.

And section 9.1.5.1 Subsystem Clocking:

1588 reference clock, CPTS_RFT_CLK (250 MHz) and RGMII (250 MHz) reference clocks are provided
by any of the Video-0/Video-1/Video_clk2/Audio/L3 PLLs as shown in Figure 9-2.

So, the default source for 1588 reference clock (cpts_rft_clk_ck) is from the VIDEO0 PLL (video0_dpll_ck). The other options are: VIDEO1 PLL (video1_dpll_ck), AUDIO PLL (audio_dpll_ck), HDMI PLL  and L3 PLL.

Do you actually need to change the default VIDEO0 PLL source to another source?

BR
Pavel

Hi Pavel,

Thanks for elaborate response. The document which you referred(DM814x Technical reference manual). I could not download. Can you share the link.

I tried some links but link is expired.Sorry for Inconvienence.

Regards,

Ashwath

Ashwath,

This is the link to the DM814x TRM:

http://www.ti.com/lit/ug/sprugz8d/sprugz8d.pdf

Regards,
Pavel

Hi Pavel,

According to my-understanding from the above discussion PLL_VIDEO0_OUT acts as default reference clock source for cpts_ref_clock which operates at 250Mhz.

Actually we wanted to change PLL_VIDEO0_OUT to change to read from hardware cpsw register directly by using get_clock_time () or to read directly  read from real-time-clock.

Is there possibility to achieve the change mentioned above.

So that we can achieve smooth control and finer access to cpts_rft_clk.

Regards,

Ashwath

Ashwath,

In EZSDK 5.05.02.00 / PSP 04.04.00.01, the source clock for cpts_rft_clk_ck is audio_dpll_ck (250MHz). Other options are:

video0_dpll_ck (250MHz)

video1_dpll_ck (20MHz)

hdmi_dpll_muxout_ck (270MHz)

l3_dpll_ck (200MHz)

BR
Pavel

Hi Pavel,

Thanks for all your input. So now since we are working with video-streaming we will concentrate on video0_dpll_ck at 250MHz.

Can  you share the small code-snippet to change the clock to video0_dpll_ck at 250MHz..

Weather that code change needs to modified in kernel-source if so which file of the source.

Best Regards,

Ashwath

Ashwath,

Refer to the link below:

http://processors.wiki.ti.com/index.php/TI81XX_PSP_PM_CLOCK_FRAMEWORK_User_Guide#Change_clock_Parent

Regards,
Pavel

Hi Pavel,

Thanks for the link,

Here is my code snippet for changing the parent clock to video0_dpll_clk....

 struct clk  *clk, new_parent;

  unsigned long rounded_rate;

clk = clk_get(NULL, "mcasp1_fck");
 
new_parent = clk_get(NULL, "video0_dpll_ck");
 
ret = clk_set_parent(clk, new_parent);

Now changing the clock rate of new clock "video0_dpll_ck" to 250MHz

rounded_rate = clk_round_rate(clk, 250); 

Now after making above change new clock will opearate 250Mhz.

Weather the above changes are fine??

In which file of kernel source Clock data structure struct clk is present?

Best Regards,

Ashwath 

Ashwath,

Here are some examples:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/197142/704160.aspx#704160

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/191218/712521.aspx#712521

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/272923/953418.aspx

In your case, you do not need to set the video0_dpll_ck to 250MHz, it is by default.

clkp = clk_get(NULL, "cpts_rft_clk_ck");

new_parent = clk_get(NULL,"video0_dpll_ck");

Regards,
Pavel

Ashwath,

Other option is to modify the u-boot source, not linux kernel source. In file ti-ezsdk_dm814x-evm_5_05_02_00/board-support/u-boot-2010.06-psp04.04.00.01/board/ti/ti8148/evm.c

/*
 * Basic board specific setup
 */
int board_init(void)
{
    u32 regVal;

    /* Do the required pin-muxing before modules are setup */
    set_muxconf_regs();

    nor_pad_config_mux();

    /* setup RMII_REFCLK to be sourced from audio_pll */
    __raw_writel(0x4, RMII_REFCLK_SRC);

You can modify the RMII_REFCLK, like:

 __raw_writel(0x0, RMII_REFCLK_SRC);  ---> to be sourced from VIDEO0_PLL_OUT

 For other options, see DM814x TRM, Table 2-189. RMII_REFCLK_SRC Register Field Descriptions.

Regards,
Pavel

Hi Pavel,

Thanks for the code snippet. I am able to change the clock to VIDEO0_PLL_OUT. 

Now is there any possibility or option to set this clock as the default system clock.  I am asking this because in our gstreamer - application using Qt framework I need to populate or run-pipeline using the clock that is being used by PTP. Because by default gstreamer will use default system clock for running the pipeline not the ptp clock.

To summarize if we can set  VIDEO0_PLL_OUT clcok as default system clock then it as good as gstremaer pipeline using PTP clock for streaming.

Can you share any-code snippet or link or suggestion to achieve this. I am thankfull to you pavel.

Best Regards,

Ashwath

Hi Pavel,

Thanks for the code snippet. I am able to change the clock to VIDEO0_PLL_OUT. 

Now is there any possibility or option to set this clock as the default system clock.  I am asking this because in our gstreamer - application using Qt framework I need to populate or run-pipeline using the clock that is being used by PTP. Because by default gstreamer will use default system clock for running the pipeline not the ptp clock.

To summarize if we can set  VIDEO0_PLL_OUT clcok as default system clock then it as good as gstremaer pipeline using PTP clock for streaming.

Can you share any-code snippet or link or suggestion to achieve this. I am thankfull to you pavel.

Best Regards,

Ashwath

Ashwath,

ashwath hebbar said:

Now is there any possibility or option to set this clock as the default system clock.

ashwath hebbar said:

To summarize if we can set  VIDEO0_PLL_OUT clcok as default system clock

No, I do not think you can set theVIDEO0_PLL_OUT clock as a default DM814x system clock. The DM814x system clock can be sourced from main device oscillator (DEVOSC) (20MHz) and auxiliary device oscillator (AUXOSC) (20 - 30 MHz).

See DM814x datasheet, 7.4 Clocking, Figure 7-6. System Clocking Overview, 7.4.1 Device (DEV) and Auxiliary (AUX) Clock Inputs.

Regards,
Pavel

Hi Pavel,

Thanks for your time. Let me get back to you in case of querrys on this.

Best Regards,

Ashwath