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Details about AM335x External DMA Interrupt Pin

Prad1
Genius 3825 points


Hi,

We are using XDMA_EVENT_INTR0/1 pins as external interrupt to DMA,
but we couldn't find details about the External DMA Interrupt Pin in the AM335x manual.
Please let us know if there is any details about the XDMA_EVENT_INTR0/1 pin's Spec.

1. We would like to confirm that in case if these pins are used to trigger event to the DMA,
　　will it be sensitive to the rising edge signal?

2. When an interrupt is received through this external pin
　　which register should be used to clear the interrupt?
　　or else is it necessary to clear the interrupt or is it automatically cleared?

We have a problem in our application,
the interrupt service routine is executed twice for a single XDMA_EVENT_INTR1 interrupt
so we would like to know if it is necessary to clear the interrupts in this case.

Best Regards,
Prad

  • 0
    TI__Guru**** 393215 points
    Hi Prad,
     
    This has already been covered in this thread: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/297029.aspx. To summarize, these pins are directly connected both to the DMA subsystem and to the INTC. If used as interrupts to the INTC they are level-sensitive. Perhaps this is why your ISR is being executed twice. If you want an edge-sensitive interrupt you can reconfigure this pin to GPIO. GPIO interrupts can be programmed to be edge-sensitive on either rising or falling edge.
  • 0 in reply to Biser Gatchev-XID
    Genius 3825 points

    Hi Biser,

    Thank you.

    You mentioned "If used as interrupts to the INTC they are level-sensitive"
    but we are using this pin as External DMA Interrupt Pin.

    The thread you mentioned has a comment as below:

    If they are using it as an interrupt to the ARM then it will be level sensitive. There is no additional logic between the pin
    and the interrupt hardware, so it will behave as the interrupt section that you referenced above states.

    If they are using it as a trigger event to the DMA then it will be edge triggered at the DMA.

    And one more thread mentions as below.

    http://e2e.ti.com/support/arm/sitara_arm/f/791/p/188447/738182.aspx#738182
    for those who wonder, XDMA_EVT_INTR0 has worked for me but the event can be generated on rising edge only
    (I was using falling edge, never worked no matter the config was)

    In our case we are also using XDMA_EVT_INTRx pin to trigger DMA and
    it seems the event is generated on rising edge.
    We wanted to make sure if our findings(rising edge triggered) is correct.

    And regarding the interrupt caused due to the XDMA_EVT_INTRx pin,
    is it necessary to clear the interrupt, we didn't find any details about this in the manual.

    Please let me know if there is any reference on XDMA_EVT_INTRx pins.

    Best Regards,
    Prad

  • 0 in reply to Prad1
    TI__Guru**** 393215 points
    Hi Prad,
     
    Yes, rising edge is correct. About the interrupt: As mentioned somewhere above this pin goes both to the INTC and the DMA. If the interrupt is not needed it can be disabled in the INTC. Details on the ARM INTC can be found on www.arm.com
  • 0 in reply to Biser Gatchev-XID
    Genius 3825 points

    Hi Biser,

    Thank you.
    I understood the External DMA Interrupt Pin is Rising Edge sensitive.

    I am sorry to bother you once again, I am little bit confused about the interrupt.

    As per you information this "External Interrupt" pin goes to both INTC and the DMA,
    so if we use it as a trigger event to the DMA,
    do we need to clear the corresponding interrupt number in the INTC module also?

    Best Regards
    Prad.

  • 0 in reply to Prad1
    TI__Guru**** 393215 points
    Rather this interrupt should be disabled. I don't have the datasheet of the INTC and cannot say how exactly.
  • 0 in reply to Biser Gatchev-XID
    Genius 3825 points

    Thank you.

    I am sorry, currently I don't have have the AM335x board to check about this topic
    so I need to confirm it on the basis of the documents.

    Regarding disabling interrupt on the INTC module,
    how about the below assumption?

    The interrupts(Chapter 6) section in the Manual(SPRUH73I) mentions
    about Masking the INTC interrupts "INTC_MIRn interrupt mask register".

    And as per "Table 6-1. ARM Cortex-A8 Interrupts" in the manual
    Interrupt Number of XDMA_EVENT_INTR0/1 is 123/124,
    so will it be OK if we mask these interrupt numbers inorder to
    disable the interrupt and allow only "trigger event to the DMA".

    Regards
    Prad

  • 0 in reply to Prad1
    TI__Guru**** 393215 points
    Absolutely, that's it! I knew I had seen it somewhere. Why was I looking for the iterrupt controller regusters in the MPU chapter, I can't guess. Thanks for highlighting this! I'll surely remember where to look now.