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AM335x SYSBOOT pins latch timing

Daisuke Maeda
Guru 20205 points

SYSBOOT[15:0] inputs are latched on the rising edge of PWRONRSTn. Are there the setup time and hold time?

Best regards,

Daisuke

 

  • 0
    TI__Guru**** 393215 points
    Hi Daisuke,
     
    Quoting from another post on this topic:
     
    The PWRONRSTn terminal may need to be held low long enough allow the SYSBOOT inputs to be pulled to their valid logic levels. Therefore, the minimum reset time also has a system dependency related to pull-up/pull-down resistors values and respective signal trace capacitance of each SYSBOOT input.
     
     
  • 0 in reply to Biser Gatchev-XID
    Guru 20205 points

    Hi Biser,

    Thank you for your reply.

    The PWRONRSTn should be held low long enough on our customer boards because the PGOOD of TPS65217C with 20ms delay is input. However, after the SYSBOOT inputs were latched, they are not held to their valid logic levels.

    After the PWRONRSTn was released, how long must the SYSBOOT inputs be held to their valid logic levels?

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Guru**** 393215 points
    This isn't stated anywhere in the documentation. There is a simple measurement you can do: If you tie SYS_BOOT[5] = 1 then you can measure the time from PORz rising edge to first edge of clock appearing on the CLKOUT1 pin. This would mean that the SYS_BOOT value is latched and processed, and will be the maximum hold time for SYS_BOOT pins.
  • 0 in reply to Biser Gatchev-XID
    Guru 20205 points

    Hi Biser,

    Thank you for your reply.

    Best regards,

    Daisuke