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Hi All,
I'm using a custom board based on AM33x EVM. The processor is DRA608 J5(similar to AM335x). I did
make tisdk_am335x-evm_defconfig and make, generated images. I flashed the images onto NOR using uboot.
when it boots I get print, "starting kernel ... " from "uboot". There afterwards it hangs. What should i do? what can be the reason?
Regards,
Gangadhar
prints
U-Boot# loadx 0x80200000
## Ready for binary (xmodem) download to 0x80200000 at 115200 bps...
CxyzModem - CRC mode, 32171(SOH)/0(STX)/0(CAN) packets, 3 retries
## Total Size = 0x003ed460 = 4117600 Bytes
U-Boot# loadx 0x80F80000
## Ready for binary (xmodem) download to 0x80F80000 at 115200 bps...
CxyzModem - CRC mode, 264(SOH)/0(STX)/0(CAN) packets, 5 retries
## Total Size = 0x000081d3 = 33235 Bytes
U-Boot# bootz 0x80200000 - 0x80F80000
Kernel image @ 0x80200000 [ 0x000000 - 0x3ed460 ]
## Flattened Device Tree blob at 80f80000
Booting using the fdt blob at 0x80f80000
Loading Device Tree to 8f32a000, end 8f3351d2 ... OK
Starting kernel ...
I've modified my dts/dtb file for my board.
Regards,
Gangadhar
Hi Gangadhar,
I will contact the factory team about support for the processor you are using.
thankyou Biser. I tried with two sets of dts file.
1. 1st dts; retaining only uarts from am335x-evm.dts , adding nor flash to it. I've attached this one.
2. 2nd dts: completely changed with pin mux for my custom board. I've attached this dts as well as the pin mux file.
Please see it.
Regards,
Gangadhar
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am33xx.dtsi"
/ {
model = "TI AM335x EVM";
compatible = "ti,am335x-evm", "ti,am33xx";
cpus {
cpu@0 {
cpu0-supply = <&vdd1_reg>;
};
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
vdd1_reg: fixedregulator-dvp1_1v26_sw {
/* VDD_MPU voltage */
compatible = "regulator-fixed";
regulator-name = "vdd_mpu";
regulator-min-microvolt = <1260000>;
regulator-max-microvolt = <1260000>;
regulator-boot-on;
regulator-always-on;
};
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = "default";
pinctrl-0 = <&clkout2_pin>;
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
uart1_pins_default: pinmux_uart1_pins_default {
pinctrl-single,pins = <
0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
>;
};
uart1_pins_sleep: pinmux_uart1_pins_sleep {
pinctrl-single,pins = <
0x178 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x17C (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x180 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x184 (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = <
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
>;
};
norflash_pins: norflash_pins {
pinctrl-single,pins = <
/*Data lines*/
0x0 (INPUT_EN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (INPUT_EN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (INPUT_EN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (INPUT_EN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (INPUT_EN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (INPUT_EN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (INPUT_EN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (INPUT_EN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x20 (INPUT_EN | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */
0x24 (INPUT_EN | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */
0x28 (INPUT_EN | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */
0x2c (INPUT_EN | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */
0x30 (INPUT_EN | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */
0x34 (INPUT_EN | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */
0x38 (INPUT_EN | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */
0x3c (INPUT_EN | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */
/*Addr lines*/
0xA0 (PIN_INPUT | MUX_MODE7) /* lcd_data0.gpio2[6]*/
0xA4 (PIN_INPUT | MUX_MODE1) /* lcd_data1.gpmc_a1_mux1*/
0xA8 (PIN_INPUT | MUX_MODE1) /* lcd_data2.gpmc_a2_mux1*/
0xAC (PIN_INPUT | MUX_MODE1) /* lcd_data3.gpmc_a3_mux1*/
0xB0 (PIN_INPUT | MUX_MODE1) /* lcd_data4.gpmc_a4_mux1*/
0xB4 (PIN_INPUT | MUX_MODE1) /* lcd_data5.gpmc_a5_mux1*/
0xB8 (PIN_INPUT | MUX_MODE1) /* lcd_data6.gpmc_a6_mux1*/
0xBC (PIN_INPUT | MUX_MODE1) /* lcd_data7.gpmc_a7_mux1*/
0xe0 (PIN_INPUT | MUX_MODE1) /* lcd_vsync.gpmc_a8_mux1*/
0xe4 (PIN_INPUT | MUX_MODE1) /* lcd_hsync.gpmc_a9_mux1*/
0xe8 (PIN_INPUT | MUX_MODE1) /* lcd_pclk.gpmc_a10_mux1*/
0xec (PIN_INPUT | MUX_MODE1) /* lcd_ac_bias_en.gpmc_a11_mux1*/
0xC0 (PULL_DISABLE | MUX_MODE1) /* lcd_data8.gpmc_a12*/
0xC4 (PULL_DISABLE | MUX_MODE1) /* lcd_data9.gpmc_a13*/
0xC8 (PULL_DISABLE | MUX_MODE1) /* lcd_data10.gpmc_a14*/
0xCC (PULL_DISABLE | MUX_MODE1) /* lcd_data11.gpmc_a15*/
0xD0 (PULL_DISABLE | MUX_MODE1) /* lcd_data12.gpmc_a16_mux1*/
0xD4 (PULL_DISABLE | MUX_MODE1) /* lcd_data13.gpmc_a17_mux1*/
0xD8 (PULL_DISABLE | MUX_MODE1) /* lcd_data14.gpmc_a18_mux1*/
0xDC (PULL_DISABLE | MUX_MODE1) /* lcd_data15.gpmc_a19_mux1*/
0xF0 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*mmc0_dat3.gpmc_a20_mux1*/
0xF4 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*mmc0_dat2.gpmc_a21_mux1*/
0xF8 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*mmc0_dat1.gpmc_a22_mux1*/
0xFC (PIN_OUTPUT_PULLUP | MUX_MODE1) /*mmc0_dat0.gpmc_a23_mux1*/
0x100 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*mmc0_clk.gpmc_a24_mux1*/
/*Control lines*/
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x7c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x94 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */
>;
};
};
ocp {
uart0: serial@44e09000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
uart1: serial@48022000 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart1_pins_default>;
pinctrl-1 = <&uart1_pins_sleep>;
status = "okay";
};
gpmc: gpmc@50000000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&norflash_pins>;
ranges = <0 0 0x08000000 0x02000000>; /* CS0: NOR */
nor@0,0 {
compatible = "cfi-flash";
linux,mtd-name= "amd,s29gl256s";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0 0x02000000>;
bank-width = <2>;
gpmc,mux-add-data;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <186>;
gpmc,cs-wr-off-ns = <186>;
gpmc,adv-on-ns = <12>;
gpmc,adv-rd-off-ns = <48>;
gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>;
gpmc,we-on-ns = <54>;
gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <114>;
gpmc,page-burst-access-ns = <6>;
gpmc,bus-turnaround-ns = <12>;
gpmc,cycle2cycle-delay-ns = <18>;
gpmc,wr-data-mux-bus-ns = <90>;
gpmc,wr-access-ns = <186>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
partition@0 {
label = "uboot";
reg = <0 0x80000>;
};
partition@0x80000 {
label = "1st-copy-uboot-env";
reg = <0x80000 0x40000>;
};
partition@0xA0000 {
label = "2nd-copy-uboot-env";
reg = <0xA0000 0x40000>;
};
partition@0xC0000 {
label = "linux-kernel";
reg = <0xC0000 0x400000>;
};
partition@0x4C0000 {
label = "userland";
reg = <0x4C0000 0x1B40000>;
};
};
};
};
};
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am33xx.dtsi"
/ {
model = "DVP1 DRA608 J5 Echo";
compatible = "ti,am335x-evm", "ti,am33xx";
cpus {
cpu@0 {
cpu0-supply = <&vdd1_reg>;
};
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
vdd1_reg: fixedregulator-dvp1_1v26_sw {
/* VDD_MPU voltage */
compatible = "regulator-fixed";
regulator-name = "vdd_mpu";
regulator-min-microvolt = <1260000>;
regulator-max-microvolt = <1260000>;
regulator-boot-on;
regulator-always-on;
};
vdd2_reg: fixedregulator-dvp1_1v1_sw {
/* VDD_CORE voltage */
compatible = "regulator-fixed";
regulator-name = "vdd_core";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
dvp1_3v3_sw: fixedregulator-dvp1_3v3_sw {
compatible = "regulator-fixed";
regulator-name = "dvp1_3v3_sw";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
am33xx_pinmux: pinmux@44e10800 {
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
0x170 (PIN_INPUT | MUX_MODE3) /* uart0_rxd.i2c2_sda */
0x174 (PIN_INPUT | MUX_MODE3) /* uart0_txd.i2c2_scl */
>;
};
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = <
0x150 (PIN_INPUT | MUX_MODE0) /* spi0_sclk.spi0_sclk */
0x154 (PIN_INPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
0x158 (PIN_INPUT | MUX_MODE7) /* spi0_d1.gpio0[4] */
0x15C (PIN_INPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0[6] */
>;
};
dcan0_pins: pinmux_dcan0_pins{
pinctrl-single,pins = <
0x178 (PULL_DISABLE | MUX_MODE2) /*uart1_ctsn.dcan0_tx_mux2 */
0x17C (PIN_INPUT | MUX_MODE2) /*uart1_rtsn.dcan0_rx_mux2 */
>;
};
uart0_pins: pinmux_uart0_pins {
/*Not used*/
pinctrl-single,pins = <
0x168 (PIN_INPUT | MUX_MODE7) /*uart0_ctsn.gpio1[8] */
0x16c (PIN_INPUT | MUX_MODE7) /*uart0_rtsn.gpio1[9] */
>;
};
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
0x180 (PIN_INPUT | MUX_MODE0) /* uart1_rxd.uart1_rxd */
0x184 (PULL_DISABLE | MUX_MODE0) /* uart1_txd.uart1_txd */
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
0x12C (INPUT_EN | MUX_MODE1) /*mii1_txclk.uart2_rxd */
0x130 (INPUT_EN | MUX_MODE1) /*mii1_rxclk.uart2_txd */
>;
};
uart5_pins: pinmux_uart5_pins {
pinctrl-single,pins = <
0x10C (INPUT_EN | MUX_MODE5) /* mii1_crs.uart5_ctsn */
0x110 (PIN_OUTPUT_PULLDOWN | MUX_MODE5) /* mii1_rxerr.uart5_rtsn */
0x148 (PIN_OUTPUT_PULLUP | MUX_MODE2) /* mdio_data.uart5_rxd_mux3 */
0x14C (PIN_OUTPUT_PULLUP | MUX_MODE2) /* mdio_clk.uart5_txd_mux3 */
>;
};
usb0_pins: pinmux_usb0_pins {
pinctrl-single,pins = <
0x21C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
>;
};
norflash_pins: norflash_pins {
pinctrl-single,pins = <
/*Data lines*/
0x0 (INPUT_EN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (INPUT_EN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (INPUT_EN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (INPUT_EN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (INPUT_EN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (INPUT_EN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (INPUT_EN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (INPUT_EN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x20 (INPUT_EN | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */
0x24 (INPUT_EN | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */
0x28 (INPUT_EN | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */
0x2c (INPUT_EN | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */
0x30 (INPUT_EN | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */
0x34 (INPUT_EN | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */
0x38 (INPUT_EN | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */
0x3c (INPUT_EN | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */
/*Addr lines*/
0xA0 (PIN_INPUT | MUX_MODE7) /* lcd_data0.gpio2[6]*/
0xA4 (PIN_INPUT | MUX_MODE1) /* lcd_data1.gpmc_a1_mux1*/
0xA8 (PIN_INPUT | MUX_MODE1) /* lcd_data2.gpmc_a2_mux1*/
0xAC (PIN_INPUT | MUX_MODE1) /* lcd_data3.gpmc_a3_mux1*/
0xB0 (PIN_INPUT | MUX_MODE1) /* lcd_data4.gpmc_a4_mux1*/
0xB4 (PIN_INPUT | MUX_MODE1) /* lcd_data5.gpmc_a5_mux1*/
0xB8 (PIN_INPUT | MUX_MODE1) /* lcd_data6.gpmc_a6_mux1*/
0xBC (PIN_INPUT | MUX_MODE1) /* lcd_data7.gpmc_a7_mux1*/
0xe0 (PIN_INPUT | MUX_MODE1) /* lcd_vsync.gpmc_a8_mux1*/
0xe4 (PIN_INPUT | MUX_MODE1) /* lcd_hsync.gpmc_a9_mux1*/
0xe8 (PIN_INPUT | MUX_MODE1) /* lcd_pclk.gpmc_a10_mux1*/
0xec (PIN_INPUT | MUX_MODE1) /* lcd_ac_bias_en.gpmc_a11_mux1*/
0xC0 (PULL_DISABLE | MUX_MODE1) /* lcd_data8.gpmc_a12*/
0xC4 (PULL_DISABLE | MUX_MODE1) /* lcd_data9.gpmc_a13*/
0xC8 (PULL_DISABLE | MUX_MODE1) /* lcd_data10.gpmc_a14*/
0xCC (PULL_DISABLE | MUX_MODE1) /* lcd_data11.gpmc_a15*/
0xD0 (PULL_DISABLE | MUX_MODE1) /* lcd_data12.gpmc_a16_mux1*/
0xD4 (PULL_DISABLE | MUX_MODE1) /* lcd_data13.gpmc_a17_mux1*/
0xD8 (PULL_DISABLE | MUX_MODE1) /* lcd_data14.gpmc_a18_mux1*/
0xDC (PULL_DISABLE | MUX_MODE1) /* lcd_data15.gpmc_a19_mux1*/
0xF0 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*mmc0_dat3.gpmc_a20_mux1*/
0xF4 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*mmc0_dat2.gpmc_a21_mux1*/
0xF8 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*mmc0_dat1.gpmc_a22_mux1*/
0xFC (PIN_OUTPUT_PULLUP | MUX_MODE1) /*mmc0_dat0.gpmc_a23_mux1*/
0x100 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*mmc0_clk.gpmc_a24_mux1*/
/*Control lines*/
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x7c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x94 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */
>;
};
mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
0x44 (INPUT_EN | MUX_MODE3) /* gpmc_a1.mmc2_dat0_mux0 */
0x48 (INPUT_EN | MUX_MODE3) /* gpmc_a2.mmc2_dat1_mux0 */
0x4C (INPUT_EN | MUX_MODE3) /* gpmc_a3.mmc2_dat2_mux0 */
0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3_mux0*/
0x58 (INPUT_EN | MUX_MODE3) /* gpmc_a6.mmc2_dat4_mux0 */
0x5C (INPUT_EN | MUX_MODE3) /* gpmc_a7.mmc2_dat5_mux0 */
0x60 (INPUT_EN | MUX_MODE3) /* gpmc_a8.mmc2_dat6_mux0 */
0x64 (INPUT_EN | MUX_MODE3) /* gpmc_a9.mmc2_dat7_mux0 */
0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd_mux0 */
0x8C (INPUT_EN | MUX_MODE3) /* gpmc_clk.mmc2_clk_mux0 */
0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0[31]*/
>;
};
};
ocp {
uart1: serial@48022000 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
uart2: serial@48024000 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
uart5: serial@481aa000 {
pinctrl-names = "default";
pinctrl-0 = <&uart5_pins>;
status = "okay";
};
i2c0: i2c@44e0b000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
clock-frequency = <400000>;
ipod: ipod@10 {
reg = <0x10>;
};
};
musb: usb@47400000 {
status = "okay";
control@44e10000 {
status = "okay";
};
usb-phy@47401300 {
status = "okay";
};
usb@47401000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins>;
};
dma-controller@07402000 {
status = "okay";
};
};
i2c2: i2c@4819c000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
clock-frequency = <400000>;
audio: audio@C5 {
reg = <0xC5>;
};
hero: hero@C6 {
reg = <0xC6>;
};
};
spi0: spi@48030000 {
/*4-line Display*/
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
clock-frequency = <400000>;
status = "okay";
};
dcan0: d_can@481cc000 {
pinctrl-names = "default";
pinctrl-0 = <&dcan0_pins>;
status = "okay";
};
elm: elm@48080000 {
status = "okay";
};
gpmc: gpmc@50000000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&norflash_pins>;
ranges = <0 0 0x08000000 0x02000000>; /* CS0: NOR */
nor@0,0 {
compatible = "cfi-flash";
linux,mtd-name= "amd,s29gl256s";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0 0x02000000>;
bank-width = <2>;
gpmc,mux-add-data;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <186>;
gpmc,cs-wr-off-ns = <186>;
gpmc,adv-on-ns = <12>;
gpmc,adv-rd-off-ns = <48>;
gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>;
gpmc,we-on-ns = <54>;
gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <114>;
gpmc,page-burst-access-ns = <6>;
gpmc,bus-turnaround-ns = <12>;
gpmc,cycle2cycle-delay-ns = <18>;
gpmc,wr-data-mux-bus-ns = <90>;
gpmc,wr-access-ns = <186>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
partition@0 {
label = "uboot";
reg = <0 0x80000>;
};
partition@0x80000 {
label = "1st-copy-uboot-env";
reg = <0x80000 0x40000>;
};
partition@0xA0000 {
label = "2nd-copy-uboot-env";
reg = <0xA0000 0x40000>;
};
partition@0xC0000 {
label = "linux-kernel";
reg = <0xC0000 0x400000>;
};
partition@0x4C0000 {
label = "userland";
reg = <0x4C0000 0x1B40000>;
};
};
};
mmc2: mmc@481d8000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&dvp1_3v3_sw>;
bus-width = <8>;
ti,non-removable;
cap-mmc-dual-data-rate;
};
};
};
&edma {
ti,edma-xbar-event-map = <1 12
2 13>;
};
#ifndef _MUX_H_
#define _MUX_H_
/*
* MODE0 - Mux Mode 0
* MODE1 - Mux Mode 1
* MODE2 - Mux Mode 2
* MODE3 - Mux Mode 3
* MODE4 - Mux Mode 4
* MODE5 - Mux Mode 5
* MODE6 - Mux Mode 6
* MODE7 - Mux Mode 7
* IDIS - Receiver disabled
* IEN - Receiver enabled
* PD - Internal pull-down
* PU - Internal pull-up
* OFF - Internal pull disabled
*/
#define MODE0 0
#define MODE1 1
#define MODE2 2
#define MODE3 3
#define MODE4 4
#define MODE5 5
#define MODE6 6
#define MODE7 7
#define IDIS (0 << 5)
#define IEN (1 << 5)
#define PD (0 << 3)
#define PU (2 << 3)
#define OFF (1 << 3)
/*
* To get the physical address the offset has
* to be added to AM335X_CTRL_BASE
*/
#define CONTROL_PADCONF_GPMC_AD0 0x0800
#define CONTROL_PADCONF_GPMC_AD1 0x0804
#define CONTROL_PADCONF_GPMC_AD2 0x0808
#define CONTROL_PADCONF_GPMC_AD3 0x080C
#define CONTROL_PADCONF_GPMC_AD4 0x0810
#define CONTROL_PADCONF_GPMC_AD5 0x0814
#define CONTROL_PADCONF_GPMC_AD6 0x0818
#define CONTROL_PADCONF_GPMC_AD7 0x081C
#define CONTROL_PADCONF_GPMC_AD8 0x0820
#define CONTROL_PADCONF_GPMC_AD9 0x0824
#define CONTROL_PADCONF_GPMC_AD10 0x0828
#define CONTROL_PADCONF_GPMC_AD11 0x082C
#define CONTROL_PADCONF_GPMC_AD12 0x0830
#define CONTROL_PADCONF_GPMC_AD13 0x0834
#define CONTROL_PADCONF_GPMC_AD14 0x0838
#define CONTROL_PADCONF_GPMC_AD15 0x083C
#define CONTROL_PADCONF_GPMC_A0 0x0840
#define CONTROL_PADCONF_GPMC_A1 0x0844
#define CONTROL_PADCONF_GPMC_A2 0x0848
#define CONTROL_PADCONF_GPMC_A3 0x084C
#define CONTROL_PADCONF_GPMC_A4 0x0850
#define CONTROL_PADCONF_GPMC_A5 0x0854
#define CONTROL_PADCONF_GPMC_A6 0x0858
#define CONTROL_PADCONF_GPMC_A7 0x085C
#define CONTROL_PADCONF_GPMC_A8 0x0860
#define CONTROL_PADCONF_GPMC_A9 0x0864
#define CONTROL_PADCONF_GPMC_A10 0x0868
#define CONTROL_PADCONF_GPMC_A11 0x086C
#define CONTROL_PADCONF_GPMC_WAIT0 0x0870
#define CONTROL_PADCONF_GPMC_WPN 0x0874
#define CONTROL_PADCONF_GPMC_BEN1 0x0878
#define CONTROL_PADCONF_GPMC_CSN0 0x087C
#define CONTROL_PADCONF_GPMC_CSN1 0x0880
#define CONTROL_PADCONF_GPMC_CSN2 0x0884
#define CONTROL_PADCONF_GPMC_CSN3 0x0888
#define CONTROL_PADCONF_GPMC_CLK 0x088C
#define CONTROL_PADCONF_GPMC_ADVN_ALE 0x0890
#define CONTROL_PADCONF_GPMC_OEN_REN 0x0894
#define CONTROL_PADCONF_GPMC_WEN 0x0898
#define CONTROL_PADCONF_GPMC_BEN0_CLE 0x089C
#define CONTROL_PADCONF_LCD_DATA0 0x08A0
#define CONTROL_PADCONF_LCD_DATA1 0x08A4
#define CONTROL_PADCONF_LCD_DATA2 0x08A8
#define CONTROL_PADCONF_LCD_DATA3 0x08AC
#define CONTROL_PADCONF_LCD_DATA4 0x08B0
#define CONTROL_PADCONF_LCD_DATA5 0x08B4
#define CONTROL_PADCONF_LCD_DATA6 0x08B8
#define CONTROL_PADCONF_LCD_DATA7 0x08BC
#define CONTROL_PADCONF_LCD_DATA8 0x08C0
#define CONTROL_PADCONF_LCD_DATA9 0x08C4
#define CONTROL_PADCONF_LCD_DATA10 0x08C8
#define CONTROL_PADCONF_LCD_DATA11 0x08CC
#define CONTROL_PADCONF_LCD_DATA12 0x08D0
#define CONTROL_PADCONF_LCD_DATA13 0x08D4
#define CONTROL_PADCONF_LCD_DATA14 0x08D8
#define CONTROL_PADCONF_LCD_DATA15 0x08DC
#define CONTROL_PADCONF_LCD_VSYNC 0x08E0
#define CONTROL_PADCONF_LCD_HSYNC 0x08E4
#define CONTROL_PADCONF_LCD_PCLK 0x08E8
#define CONTROL_PADCONF_LCD_AC_BIAS_EN 0x08EC
#define CONTROL_PADCONF_MMC0_DAT3 0x08F0
#define CONTROL_PADCONF_MMC0_DAT2 0x08F4
#define CONTROL_PADCONF_MMC0_DAT1 0x08F8
#define CONTROL_PADCONF_MMC0_DAT0 0x08FC
#define CONTROL_PADCONF_MMC0_CLK 0x0900
#define CONTROL_PADCONF_MMC0_CMD 0x0904
#define CONTROL_PADCONF_MII1_COL 0x0908
#define CONTROL_PADCONF_MII1_CRS 0x090C
#define CONTROL_PADCONF_MII1_RX_ER 0x0910
#define CONTROL_PADCONF_MII1_TX_EN 0x0914
#define CONTROL_PADCONF_MII1_RX_DV 0x0918
#define CONTROL_PADCONF_MII1_TXD3 0x091C
#define CONTROL_PADCONF_MII1_TXD2 0x0920
#define CONTROL_PADCONF_MII1_TXD1 0x0924
#define CONTROL_PADCONF_MII1_TXD0 0x0928
#define CONTROL_PADCONF_MII1_TX_CLK 0x092C
#define CONTROL_PADCONF_MII1_RX_CLK 0x0930
#define CONTROL_PADCONF_MII1_RXD3 0x0934
#define CONTROL_PADCONF_MII1_RXD2 0x0938
#define CONTROL_PADCONF_MII1_RXD1 0x093C
#define CONTROL_PADCONF_MII1_RXD0 0x0940
#define CONTROL_PADCONF_RMII1_REF_CLK 0x0944
#define CONTROL_PADCONF_MDIO 0x0948
#define CONTROL_PADCONF_MDC 0x094C
#define CONTROL_PADCONF_SPI0_SCLK 0x0950
#define CONTROL_PADCONF_SPI0_D0 0x0954
#define CONTROL_PADCONF_SPI0_D1 0x0958
#define CONTROL_PADCONF_SPI0_CS0 0x095C
#define CONTROL_PADCONF_SPI0_CS1 0x0960
#define CONTROL_PADCONF_ECAP0_IN_PWM0_OUT 0x0964
#define CONTROL_PADCONF_UART0_CTSN 0x0968
#define CONTROL_PADCONF_UART0_RTSN 0x096C
#define CONTROL_PADCONF_UART0_RXD 0x0970
#define CONTROL_PADCONF_UART0_TXD 0x0974
#define CONTROL_PADCONF_UART1_CTSN 0x0978
#define CONTROL_PADCONF_UART1_RTSN 0x097C
#define CONTROL_PADCONF_UART1_RXD 0x0980
#define CONTROL_PADCONF_UART1_TXD 0x0984
#define CONTROL_PADCONF_I2C0_SDA 0x0988
#define CONTROL_PADCONF_I2C0_SCL 0x098C
#define CONTROL_PADCONF_MCASP0_ACLKX 0x0990
#define CONTROL_PADCONF_MCASP0_FSX 0x0994
#define CONTROL_PADCONF_MCASP0_AXR0 0x0998
#define CONTROL_PADCONF_MCASP0_AHCLKR 0x099C
#define CONTROL_PADCONF_MCASP0_ACLKR 0x09A0
#define CONTROL_PADCONF_MCASP0_FSR 0x09A4
#define CONTROL_PADCONF_MCASP0_AXR1 0x09A8
#define CONTROL_PADCONF_MCASP0_AHCLKX 0x09AC
#define CONTROL_PADCONF_XDMA_EVENT_INTR0 0x09B0
#define CONTROL_PADCONF_XDMA_EVENT_INTR1 0x09B4
#define CONTROL_PADCONF_WARMRSTN 0x09B8
#define CONTROL_PADCONF_EXTINTN 0x09C0
#define CONTROL_PADCONF_TMS 0x09D0
#define CONTROL_PADCONF_TDI 0x09D4
#define CONTROL_PADCONF_TDO 0x09D8
#define CONTROL_PADCONF_TCK 0x09DC
#define CONTROL_PADCONF_TRSTN 0x09E0
#define CONTROL_PADCONF_EMU0 0x09E4
#define CONTROL_PADCONF_EMU1 0x09E8
#define CONTROL_PADCONF_RTC_PWRONRSTN 0x09F8
#define CONTROL_PADCONF_PMIC_POWER_EN 0x09FC
#define CONTROL_PADCONF_EXT_WAKEUP 0x0A00
#define CONTROL_PADCONF_RTC_KALDO_ENN 0x0A04
#define CONTROL_PADCONF_USB0_DRVVBUS 0x0A1C
#define CONTROL_PADCONF_USB1_DRVVBUS 0x0A34
#define MUX_VAL(OFFSET,VALUE)\
writel((VALUE), AM335X_CTRL_BASE + (OFFSET));
#endif
#ifndef _PINMUX_H_ #define _PINMUX_H_ /* * MODE0 - Mux Mode 0 * MODE1 - Mux Mode 1 * MODE2 - Mux Mode 2 * MODE3 - Mux Mode 3 * MODE4 - Mux Mode 4 * MODE5 - Mux Mode 5 * MODE6 - Mux Mode 6 * MODE7 - Mux Mode 7 * IDIS - Receiver disabled * IEN - Receiver enabled * PD - Internal pull-down * PU - Internal pull-up * OFF - Internal pull disabled */ #define MUX_EVM() \ /* Design Status: NO ERRORS */ MUX_VAL(CONTROL_PADCONF_GPMC_AD0, (IEN | PD | MODE0 )) /* gpmc_ad0 */\ MUX_VAL(CONTROL_PADCONF_GPMC_AD1, (IEN | PD | MODE0 )) /* gpmc_ad1 */\ MUX_VAL(CONTROL_PADCONF_GPMC_AD2, (IEN | PD | MODE0 )) /* gpmc_ad2 */\ MUX_VAL(CONTROL_PADCONF_GPMC_AD3, (IEN | PD | MODE0 )) /* gpmc_ad3 */\ MUX_VAL(CONTROL_PADCONF_GPMC_AD4, (IEN | PD | MODE0 )) /* gpmc_ad4 */\ MUX_VAL(CONTROL_PADCONF_GPMC_AD5, (IEN | PD | MODE0 )) /* gpmc_ad5 */\ MUX_VAL(CONTROL_PADCONF_GPMC_AD6, (IEN | PD | MODE0 )) /* gpmc_ad6 */\ MUX_VAL(CONTROL_PADCONF_GPMC_AD7, (IEN | PD | MODE0 )) /* gpmc_ad7 */\ MUX_VAL(CONTROL_PADCONF_GPMC_AD8, (IEN | PD | MODE0 )) /* gpmc_ad8 */\ MUX_VAL(CONTROL_PADCONF_GPMC_AD9, (IEN | PD | MODE0 )) /* gpmc_ad9 */\ MUX_VAL(CONTROL_PADCONF_GPMC_AD10, (IEN | PD | MODE0 )) /* gpmc_ad10 */\ MUX_VAL(CONTROL_PADCONF_GPMC_AD11, (IEN | PD | MODE0 )) /* gpmc_ad11 */\ MUX_VAL(CONTROL_PADCONF_GPMC_AD12, (IEN | PD | MODE0 )) /* gpmc_ad12 */\ MUX_VAL(CONTROL_PADCONF_GPMC_AD13, (IEN | PD | MODE0 )) /* gpmc_ad13 */\ MUX_VAL(CONTROL_PADCONF_GPMC_AD14, (IEN | PD | MODE0 )) /* gpmc_ad14 */\ MUX_VAL(CONTROL_PADCONF_GPMC_AD15, (IEN | PD | MODE0 )) /* gpmc_ad15 */\ MUX_VAL(CONTROL_PADCONF_GPMC_A0, (IEN | PD | MODE7 )) /* gpio1[16] */\ MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IEN | PD | MODE3 )) /* mmc2_dat0_mux0 */\ MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IEN | PD | MODE3 )) /* mmc2_dat1_mux0 */\ MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IEN | PD | MODE3 )) /* mmc2_dat2_mux0 */\ MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IEN | PD | MODE7 )) /* gpio1[20] */\ MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IEN | PD | MODE7 )) /* gpio1[21] */\ MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IEN | PD | MODE3 )) /* mmc2_dat4_mux0 */\ MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IEN | PD | MODE3 )) /* mmc2_dat5_mux0 */\ MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | PD | MODE3 )) /* mmc2_dat6_mux0 */\ MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | PD | MODE3 )) /* mmc2_dat7_mux0/rmii2_crs_dv_mux2 */\ MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IEN | PD | MODE7 )) /* gpio1[26] */\ MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IEN | PD | MODE7 )) /* gpio1[27] */\ MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | PU | MODE0 )) /* gpmc_wait0 */\ MUX_VAL(CONTROL_PADCONF_GPMC_WPN, (IEN | PU | MODE7 )) /* gpio0[31] */\ MUX_VAL(CONTROL_PADCONF_GPMC_BEN1, (IEN | PU | MODE3 )) /* mmc2_dat3_mux0 */\ MUX_VAL(CONTROL_PADCONF_GPMC_CSN0, (IEN | PU | MODE0 )) /* gpmc_csn0 */\ MUX_VAL(CONTROL_PADCONF_GPMC_CSN1, (IEN | PU | MODE7 )) /* gpio1[30] */\ MUX_VAL(CONTROL_PADCONF_GPMC_CSN2, (IEN | PU | MODE7 )) /* gpio1[31] */\ MUX_VAL(CONTROL_PADCONF_GPMC_CSN3, (IEN | PU | MODE3 )) /* mmc2_cmd_mux0 */\ MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IEN | PD | MODE3 )) /* mmc2_clk_mux0 */\ MUX_VAL(CONTROL_PADCONF_GPMC_ADVN_ALE, (IEN | PU | MODE7 )) /* gpio2[2] */\ MUX_VAL(CONTROL_PADCONF_GPMC_OEN_REN, (IDIS | PU | MODE0 )) /* gpmc_oen_ren */\ MUX_VAL(CONTROL_PADCONF_GPMC_WEN, (IEN | PU | MODE0 )) /* gpmc_wen */\ MUX_VAL(CONTROL_PADCONF_GPMC_BEN0_CLE, (IEN | PU | MODE2 )) /* timer5_mux3 */\ MUX_VAL(CONTROL_PADCONF_LCD_DATA0, (IEN | OFF | MODE7 )) /* gpio2[6] */\ MUX_VAL(CONTROL_PADCONF_LCD_DATA1, (IEN | OFF | MODE1 )) /* gpmc_a1_mux1 */\ MUX_VAL(CONTROL_PADCONF_LCD_DATA2, (IEN | OFF | MODE1 )) /* gpmc_a2_mux1 */\ MUX_VAL(CONTROL_PADCONF_LCD_DATA3, (IEN | OFF | MODE1 )) /* gpmc_a3_mux1 */\ MUX_VAL(CONTROL_PADCONF_LCD_DATA4, (IEN | OFF | MODE1 )) /* gpmc_a4_mux1 */\ MUX_VAL(CONTROL_PADCONF_LCD_DATA5, (IEN | OFF | MODE1 )) /* gpmc_a5_mux1 */\ MUX_VAL(CONTROL_PADCONF_LCD_DATA6, (IEN | OFF | MODE1 )) /* gpmc_a6_mux1 */\ MUX_VAL(CONTROL_PADCONF_LCD_DATA7, (IEN | OFF | MODE1 )) /* gpmc_a7_mux1 */\ MUX_VAL(CONTROL_PADCONF_LCD_DATA8, (IDIS | OFF | MODE1 )) /* gpmc_a12 */\ MUX_VAL(CONTROL_PADCONF_LCD_DATA9, (IDIS | OFF | MODE1 )) /* gpmc_a13 */\ MUX_VAL(CONTROL_PADCONF_LCD_DATA10, (IDIS | OFF | MODE1 )) /* gpmc_a14 */\ MUX_VAL(CONTROL_PADCONF_LCD_DATA11, (IDIS | OFF | MODE1 )) /* gpmc_a15 */\ MUX_VAL(CONTROL_PADCONF_LCD_DATA12, (IDIS | OFF | MODE1 )) /* gpmc_a16_mux1 */\ MUX_VAL(CONTROL_PADCONF_LCD_DATA13, (IDIS | OFF | MODE1 )) /* gpmc_a17_mux1 */\ MUX_VAL(CONTROL_PADCONF_LCD_DATA14, (IDIS | OFF | MODE1 )) /* gpmc_a18_mux1 */\ MUX_VAL(CONTROL_PADCONF_LCD_DATA15, (IDIS | OFF | MODE1 )) /* gpmc_a19_mux1 */\ MUX_VAL(CONTROL_PADCONF_LCD_VSYNC, (IEN | OFF | MODE1 )) /* gpmc_a8_mux1 */\ MUX_VAL(CONTROL_PADCONF_LCD_HSYNC, (IEN | OFF | MODE1 )) /* gpmc_a9_mux1 */\ MUX_VAL(CONTROL_PADCONF_LCD_PCLK, (IEN | OFF | MODE1 )) /* gpmc_a10_mux1 */\ MUX_VAL(CONTROL_PADCONF_LCD_AC_BIAS_EN, (IEN | OFF | MODE1 )) /* gpmc_a11_mux1 */\ MUX_VAL(CONTROL_PADCONF_MMC0_DAT3, (IDIS | PU | MODE1 )) /* gpmc_a20_mux1 */\ MUX_VAL(CONTROL_PADCONF_MMC0_DAT2, (IDIS | PU | MODE1 )) /* gpmc_a21_mux1 */\ MUX_VAL(CONTROL_PADCONF_MMC0_DAT1, (IDIS | PU | MODE1 )) /* gpmc_a22_mux1 */\ MUX_VAL(CONTROL_PADCONF_MMC0_DAT0, (IDIS | PU | MODE1 )) /* gpmc_a23_mux1 */\ MUX_VAL(CONTROL_PADCONF_MMC0_CLK, (IDIS | PU | MODE1 )) /* gpmc_a24_mux1 */\ MUX_VAL(CONTROL_PADCONF_MMC0_CMD, (IEN | PU | MODE7 )) /* gpio2[31] */\ MUX_VAL(CONTROL_PADCONF_MII1_COL, (IEN | PD | MODE4 )) /* mcasp1_axr2_mux1 */\ MUX_VAL(CONTROL_PADCONF_MII1_CRS, (IEN | PD | MODE5 )) /* uart5_ctsn_mux2 */\ MUX_VAL(CONTROL_PADCONF_MII1_RX_ER, (IDIS | PD | MODE5 )) /* uart5_rtsn_mux2 */\ MUX_VAL(CONTROL_PADCONF_MII1_TX_EN, (IEN | PD | MODE7 )) /* gpio3[3] */\ MUX_VAL(CONTROL_PADCONF_MII1_RX_DV, (IEN | PD | MODE4 )) /* mcasp1_aclkx_mux0 */\ MUX_VAL(CONTROL_PADCONF_MII1_TXD3, (IEN | PD | MODE4 )) /* mcasp1_fsx_mux0 */\ MUX_VAL(CONTROL_PADCONF_MII1_TXD2, (IEN | PD | MODE4 )) /* mcasp1_axr0_mux0 */\ MUX_VAL(CONTROL_PADCONF_MII1_TXD1, (IEN | PD | MODE7 )) /* gpio0[21] */\ MUX_VAL(CONTROL_PADCONF_MII1_TXD0, (IEN | PD | MODE7 )) /* gpio0[28] */\ MUX_VAL(CONTROL_PADCONF_MII1_TX_CLK, (IEN | PD | MODE1 )) /* uart2_rxd_mux0 */\ MUX_VAL(CONTROL_PADCONF_MII1_RX_CLK, (IEN | PD | MODE1 )) /* uart2_txd_mux0 */\ MUX_VAL(CONTROL_PADCONF_MII1_RXD3, (IEN | PD | MODE7 )) /* gpio2[18] */\ MUX_VAL(CONTROL_PADCONF_MII1_RXD2, (IEN | PD | MODE7 )) /* gpio2[19] */\ MUX_VAL(CONTROL_PADCONF_MII1_RXD1, (IEN | PD | MODE7 )) /* gpio2[20] */\ MUX_VAL(CONTROL_PADCONF_MII1_RXD0, (IEN | PD | MODE7 )) /* gpio2[21] */\ MUX_VAL(CONTROL_PADCONF_RMII1_REF_CLK, (IEN | PD | MODE7 )) /* gpio0[29] */\ MUX_VAL(CONTROL_PADCONF_MDIO, (IDIS | PU | MODE2 )) /* uart5_rxd_mux3 */\ MUX_VAL(CONTROL_PADCONF_MDC, (IDIS | PU | MODE2 )) /* uart5_txd_mux3 */\ MUX_VAL(CONTROL_PADCONF_SPI0_SCLK, (IEN | OFF | MODE0 )) /* spi0_sclk */\ MUX_VAL(CONTROL_PADCONF_SPI0_D0, (IEN | OFF | MODE0 )) /* spi0_d0 */\ MUX_VAL(CONTROL_PADCONF_SPI0_D1, (IEN | OFF | MODE7 )) /* gpio0[4] */\ MUX_VAL(CONTROL_PADCONF_SPI0_CS0, (IEN | OFF | MODE0 )) /* spi0_cs0 */\ MUX_VAL(CONTROL_PADCONF_SPI0_CS1, (IEN | OFF | MODE7 )) /* gpio0[6] */\ MUX_VAL(CONTROL_PADCONF_ECAP0_IN_PWM0_OUT, (IEN | OFF | MODE7 )) /* gpio0[7] */\ MUX_VAL(CONTROL_PADCONF_UART0_CTSN, (IEN | OFF | MODE7 )) /* gpio1[8] */\ MUX_VAL(CONTROL_PADCONF_UART0_RTSN, (IEN | OFF | MODE7 )) /* gpio1[9] */\ MUX_VAL(CONTROL_PADCONF_UART0_RXD, (IEN | OFF | MODE3 )) /* I2C2_SDA_mux1 */\ MUX_VAL(CONTROL_PADCONF_UART0_TXD, (IEN | OFF | MODE3 )) /* I2C2_SCL_mux1 */\ MUX_VAL(CONTROL_PADCONF_UART1_CTSN, (IDIS | OFF | MODE2 )) /* dcan0_tx_mux2 */\ MUX_VAL(CONTROL_PADCONF_UART1_RTSN, (IEN | OFF | MODE2 )) /* dcan0_rx_mux2 */\ MUX_VAL(CONTROL_PADCONF_UART1_RXD, (IEN | OFF | MODE0 )) /* uart1_rxd */\ MUX_VAL(CONTROL_PADCONF_UART1_TXD, (IDIS | OFF | MODE0 )) /* uart1_txd */\ MUX_VAL(CONTROL_PADCONF_I2C0_SDA, (IEN | OFF | MODE0 )) /* I2C0_SDA */\ MUX_VAL(CONTROL_PADCONF_I2C0_SCL, (IEN | OFF | MODE0 )) /* I2C0_SCL */\ MUX_VAL(CONTROL_PADCONF_MCASP0_ACLKX, (IEN | PD | MODE0 )) /* mcasp0_aclkx_mux0 */\ MUX_VAL(CONTROL_PADCONF_MCASP0_FSX, (IEN | PD | MODE0 )) /* mcasp0_fsx_mux0 */\ MUX_VAL(CONTROL_PADCONF_MCASP0_AXR0, (IEN | PD | MODE0 )) /* mcasp0_axr0_mux0 */\ MUX_VAL(CONTROL_PADCONF_MCASP0_AHCLKR, (IEN | PD | MODE7 )) /* gpio3[17] */\ MUX_VAL(CONTROL_PADCONF_MCASP0_ACLKR, (IEN | PD | MODE2 )) /* mcasp0_axr2_mux1 */\ MUX_VAL(CONTROL_PADCONF_MCASP0_FSR, (IEN | PD | MODE2 )) /* mcasp0_axr3_mux1 */\ MUX_VAL(CONTROL_PADCONF_MCASP0_AXR1, (IEN | PD | MODE0 )) /* mcasp0_axr1_mux0 */\ MUX_VAL(CONTROL_PADCONF_MCASP0_AHCLKX, (IEN | PD | MODE7 )) /* gpio3[21] */\ MUX_VAL(CONTROL_PADCONF_XDMA_EVENT_INTR0, (IEN | OFF | MODE2 )) /* timer4_mux1 */\ MUX_VAL(CONTROL_PADCONF_XDMA_EVENT_INTR1, (IEN | OFF | MODE4 )) /* timer7_mux1 */\ MUX_VAL(CONTROL_PADCONF_WARMRSTN, (IEN | OFF | MODE0 )) /* nRESETIN_OUT */\ MUX_VAL(CONTROL_PADCONF_EXTINTN, (IEN | OFF | MODE0 )) /* nNMI */\ MUX_VAL(CONTROL_PADCONF_TMS, (IEN | PU | MODE0 )) /* TMS */\ MUX_VAL(CONTROL_PADCONF_TDI, (IEN | PU | MODE0 )) /* TDI */\ MUX_VAL(CONTROL_PADCONF_TDO, (IDIS | PU | MODE0 )) /* TDO */\ MUX_VAL(CONTROL_PADCONF_TCK, (IEN | PU | MODE0 )) /* TCK */\ MUX_VAL(CONTROL_PADCONF_TRSTN, (IEN | PD | MODE0 )) /* nTRST */\ MUX_VAL(CONTROL_PADCONF_EMU0, (IEN | PU | MODE7 )) /* gpio3[7] */\ MUX_VAL(CONTROL_PADCONF_EMU1, (IEN | PU | MODE7 )) /* gpio3[8] */\ MUX_VAL(CONTROL_PADCONF_RTC_PWRONRSTN, (IEN | OFF | MODE0 )) /* RTC_porz */\ MUX_VAL(CONTROL_PADCONF_PMIC_POWER_EN, (IDIS | PU | MODE0 )) /* PMIC_POWER_EN */\ MUX_VAL(CONTROL_PADCONF_EXT_WAKEUP, (IEN | PD | MODE0 )) /* EXT_WAKEUP */\ MUX_VAL(CONTROL_PADCONF_RTC_KALDO_ENN, (IEN | OFF | MODE0 )) /* ENZ_KALDO_1P8V */\ MUX_VAL(CONTROL_PADCONF_USB0_DRVVBUS, (IDIS | PD | MODE0 )) /* USB0_DRVVBUS */\ MUX_VAL(CONTROL_PADCONF_USB1_DRVVBUS, (IEN | PD | MODE7 )) /* gpio3[13] */\ #endif
Hi,
The answer from the factory team is that DRA608 J5 is not supported by the Sitara team. Please contact your TI FAE for support.
Hi All,
1. If I use SDK6.0 generate uImage, run as bootm uImage on my custom board, kernel boots and I get prints.
2. If I use SDK7.0 generate uImage/zImage and run as bootm uImage - dtb or bootz zImage - dtb on my custom board , kernel does not boot and no prints. But the same images perfectly work on AM335x EVM.
What am I missing? To generate kernel I just used make tisdk_am335x-evm_defconfig and make / make uImage.
In my previous posts I've also attached the dts file that I'm using.
Regards,
Gangadhar
Hi All,
With SDK 7.0, linux - 3.12, custom board, I used early_print() to get prints. No prints from printk(), Also kernel hangs
after calling do_initcall_level() twice. Sequence: start_kernel -> rest_init() -> kernel_init() -> kernel_init_freeable() -> do_basic_setup() -> do_initcalls -> do_initcall_level()
The same image gives prints(printk()) on EVM.
1. I checked bootargs using early_print(), it's correct: console=ttyO0,115200n8 root=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M rootfstype=ext2
2. I checked my uart0 pin mux in dts file, it matches that in uboot.
3. I also tried removing uart0 pin mux in dts as it'll be initiallized in uboot, but the issue remains the same.
What am I missing?
Regards,
Gangadhar
Problem solved. I'm able to get kernel running on my custom board. I made kernel to take bootargs defined from kernel at make menuconfig --> boot option and passed earlyprintk as one of the parameters. Got prints and found that it crashes while enabling system cache, i bypassed this temporarily. Kernel came up completely.
Regards,
Gangadhar