TI DSP C6670 communication with Xilinx "vertex" FPGA SRIO (IP) GEN 2

Hi,

Earlier we have 6 DSP communication with vertex FPGA using 6- SRIO " GEN 1" links  respectively.

Now the FPGA guys have upgraded to SRIO GEN 2.

Problem we are facing :-

using the 2 DSP and FPGA communication via 2 SRIO links resp , at the first start up for DSP and FPGA both the links work fine but whenever the DSP is reset or reloads then the FPGA is not able to get the SRIO LOCK " Gets Synchronise" even though the LINK and PORT is status is OK.

This happened only with one DSP but the other DSP works fine all the time.

I tried with the other DSPs as well, only DSP 0 and DSP 5 works.

Please guide me to resolve the Issue.

Thanks, Manav

Hi Ganapathi,

Thanks for the reply.

1. Share your FPGA RapidIO Specification REV?

 ----> RapidIO Gen 2 Ver 1.7

2. DSPs SRIO configuration detail? (ports and baud rate)

----> There are 6 DSP communicating with vertex FPGA via 6 SRIO links using

       # Port 0 in 1x mode at baud rate 3.125 Gbps.

        #DSP acts as a master and FPGA operates in slave mode.

        # Only Maintenance , Nread/Nwrite, Nwrite_R transactions Direct IO are supported.

3. Have you running same code on all DSP's? 

---->Yes,  I am running the same code on all DSP's.

Regards, Manav

Hi Manav,

Please confirm your FPGA RapidIO Specification revision. i did not find the ver 1.7 on repiidIO side.

Your DSP's silicon versions are same?

Thanks,

Hi Ganapathi,

1. Correction to the FPGA RapidIO Specification revision :-

--> Its XILINX's LogiCore IP RapidIO Gen 2  designed to "RapidIO Gen 2.2" specification.

 2. DSP's silicon versions are same for "TI C6670 DSP's"

Regards,

Manav

Regards,

Manav

Hi,

In above thread you told DSP0 and DSP5 are properly communicating with FPGA, that means the DSP driver code is fine.

I think issue on your FPGA side.

Thanks,

Hi Ganapathi,

Thanks for the reply.

Yes, Among the 6 DSPs (0,5) are properly communicating with FPGA.

But the FPGA guys also replicated the same code to support the 6 SRIO Link interface.

On testing,

#1.  I have observed that remote SRIO Link (FPGA) for  DSP 0 &  DSP 5 comes UP quickly as compared to delayed link activation in DSP 1 to DSP 4, after reset and releasing the DSP image.

Even the link comes UP for DSP 1 to 4 , it is not stable. executing a transaction shows hostport(-1).

 ---> your comment/suggestion

 #2. After getting the SRIO LINK state in Working, when we use the NREAD transaction it fetches the wrong data in the DSP whereas upon debugging in the FPGA side using the chip scope tool its shows the correct 0xaddr is requested and the correct data is responded.

 ---> your comment/suggestion

#3 I have tried Executing the same NREAD transaction multiple times,

Either it gives some junk values OR I can see the error msg "No LSU available" OR unexpected  LSU Transaction Completion Status - {0 - request timed out, 4 - unsupported transaction type / invalid programming encoding for one or more LSU register fields}

 ---> your comment/suggestion

#4 How do I verify why Nread Transaction request timed out ?

#5 What physical layer status registers should I monitor to troubleshoot this problem ?

Regards,

Manav