C667x: PCIe Malformed TLP issue for "Memory Read" TLP from EP to RC

SENTHILKUMAR RAMAN

Hi,

In our custom C6672 Board we are facing a “Malformed TLP” issue whenever we issue a “Memory Read” request TLP from PCIe Endpoint to PCIe Root complex.

Test Setup: C6672 is configured as root complex and FPGA is configured as endpoint, and there is no any PCIe switch between them.

Observation:

Root Complex(C6672) configuration is mentioned in the attached “PCIe_RC_EP_ConfigurationRegisters_And_Error_Logs.docx” file.
End Point(FPGA) configuration is mentioned in the attached “PCIe_RC_EP_ConfigurationRegisters_And_Error_Logs.docx” file.
With this RC and EP configuration, PCIe link is up
From root complex we are able to read and write to end point successfully, but from the end point we are not able to read/write to the root complex
Observation when the end point fails to read/write to RC is as follows,

- Register 0x21801104 (“PCI Express Uncorrectable Error Status Register”) shows the “Malformed TLP error status” as mentioned in the attached “PCIe_RC_EP_ConfigurationRegisters_And_Error_Logs.docx” file
- Registers 0x2180111C, 0x21801120 and 0x21801124 shows the actual TLP header transmitted from the endpoint to the root complex as mentioned in the attached “PCIe_RC_EP_ConfigurationRegisters_And_Error_Logs.docx” file

We have cross verified the inbound window configuration at RC and the read request TLP header information and everything seems to be correct but still we are getting the “Malformed TLP” error.

I kindly request you to check the RC and EP configuration as mentioned in the attached files and please let us know where we are making the mistake.

With Regards,

R.Senthilkumar

PCIe_RC_EP_ConfigurationRegisters_And_Error_Logs.docx

over 10 years ago

0 Ganapathi Dhandapani95 over 10 years ago

TI__Mastermind 28085 points

Hi Senthil,

Please go through below wiki for PCIe related FAQs and Resources.

http://processors.wiki.ti.com/index.php/PCI_Express_(PCIe)_Resource_Wiki_for_Keystone_Devices

Thanks,

0 SENTHILKUMAR RAMAN over 10 years ago in reply to Ganapathi Dhandapani95

Intellectual 335 points

Hi Ganapathy,

Sorry for the delay.

That "Malformed TLP" issue is resolved, it was a bug in our end point side (FPGA) while forming the read request TLP (Reminder bits were reversely connected to Pcie core).

Now while trying the legacy INTA legacy interrupt from endpoint (FPGA) to root complex (C6678), we are facing the following issue.

When the first interrupt is given by Endpoint (FPGA), root complex (C6678) ISR is invoked properly. And the value of register "0x21800180" is 1 and once after the interrupt is serviced the value of register "0x21800180" is 0.
From the second interrupt (given by EndPoint), root complex ISR is not invoked, and the value of register "0x21800180" is always 0.
Even after we manually set the register "0x21800180" to 1, our ISR is not invoked. [Note: this manual testing of ISR always working only for the first attempt]

Our ISR function is as follows,

----------------------------------

void hwi_pcie_inta(UArg arg)
{
coreKey = Hwi_disableInterrupt(4);
*(UInt32 *)(0x21800184) = 1;
*(UInt32 *)(0x21800050) = 4; // say PCIe "interrupt is servised"

pcie_inta++;

Hwi_restoreInterrupt(4, coreKey );

}

And we are registering the interrupt handler as follows,

-------------------------------------------------------------------

CpIntc_mapSysIntToHostInt(0, 50, 32);
CpIntc_dispatchPlug(50, &event50Fxn, 50, TRUE);
CpIntc_enableHostInt(0, 32);
CpIntc_enableSysInt(0, 50);
eventId = CpIntc_getEventId(32);
Hwi_Params_init(&params);
params.arg = 32;
params.eventId = eventId;
params.enableInt = TRUE;
Hwi_create(4, &hwi_pcie_inta, &params, NULL);
Hwi_enableInterrupt(4);
Hwi_enable();

Please let me know where we are making the mistake. and if possible please provide us any TI example code for handling the PCIe legacy interrupt in C6678.

With Regards,

R.senthilkumar

0 Ganapathi Dhandapani95 over 10 years ago in reply to SENTHILKUMAR RAMAN

TI__Mastermind 28085 points

Hi,

Please take a look at section 2.14.5.1 Legacy Interrupts Reception in RC Mode on PCIe user guide and try to verify the interrupt status register is cleared or not.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/306369/1069000.aspx#1069000

Thanks,

0 bt yang over 9 years ago in reply to SENTHILKUMAR RAMAN

Prodigy 155 points

Hi, Dear R.senthilkumar:

I encounter the same issue, and my FPGA did the reversely operation after send to the core, however, C6678 cann't receive any data and express the "Malformed TLP" error sometimes.

Did the "Reminder bits" you metioned are all TLP bits? Or Payload bits?

Expecting your reply, many thanks!

With Regards,

yang

Processors

Processors forum

C667x: PCIe Malformed TLP issue for "Memory Read" TLP from EP to RC