Hi,
My FPGA-wielding coworker and I are seeing intermittent SRIO link errors in data going from a C6678 to a (Xilinx) FPGA on a custom board, even at relatively low line rates.
When the DSP sends SWRITEs containing a 32-bit up-counting sequence, the FPGA reports disparity errors within about 10 seconds and drops the link as a result. If the SWRITEs contain a fixed 64-bit pattern (specifically, 0xABCDEF0123456789) or a pseudo-random sequence (x[0]=1, x[n]=x[n-1]*0x100011, for 32-bit x[n]), we do not see this kind of problem. We can also turn on the PRBS with length 2**23-1, and go for minutes (at least) with zero bit errors in this direction. If I run a debug build of the DSP code, which causes larger gaps between packets, the 32-bit up-counting sequence works. A similar up-counting pattern from the FPGA to the DSP does not seem to cause any link problems, although I did frequently see RX TESTFAIL toggle (in SRIO_SERDES_STS) with the 2**23-1 PRBS.
We first saw these problems at 5 Gbaud, but also see them at 2.5 Gbaud. (An older board design, with a C6474 and an earlier-generation FPGA, operates well at 3.125 Gbaud -- and the layout rules were of course stricter for the new board.) 1x or 4x port width does not seem to matter. The two ends of the SRIO link are running from the same clock source, although (obviously) with different delays and different PLLs in front.
The FPGA guys here say this looks almost identical to a problem they saw with a SerDes link between FPGAs, which they solved by enabling data scrambling over that link. I understand that -- contrary to what SPRUGW1B says -- the Keystone I family does not support SRIO IDLE2 patterns or bit scrambling, so that is not an option here.
Does anyone have suggestions on how to fix this problem?
Thanks in advance,
Michael
