Hello everyone,
I'm trying to configure the memory map on my custom board using an AM389x processor (no interleaved).
I have 1 GB DDR (512MB on EMIF0 and 512MB on EMIF1).
My previous running configuration was:
#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
#define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */
#define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */
#define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */
__raw_writel(0x0, DMM_LISA_MAP__0);
__raw_writel(0x0, DMM_LISA_MAP__1);
__raw_writel(0x80600100, DMM_LISA_MAP__2);
__raw_writel(0xC0600220, DMM_LISA_MAP__3);
But checking follow links
http://processors.wiki.ti.com/index.php/EZSDK_Memory_Map#Changing_Memory_Map_For_512MB_DM816x_Board
http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/304274/1060662#1060662
https://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/294217
I think the right configuration could be:
#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
#define PHYS_DRAM_1_SIZE 0x20000000 /* 512 MB */
#define PHYS_DRAM_2 0xA0000000 /* DRAM Bank #2 */
#define PHYS_DRAM_2_SIZE 0x20000000 /* 512 MB */
__raw_writel(0x0, DMM_LISA_MAP__0);
__raw_writel(0x0, DMM_LISA_MAP__1);
__raw_writel(0x80500100, DMM_LISA_MAP__2);
__raw_writel(0xA0500200, DMM_LISA_MAP__3);
I have a lot of doubts about the values of this constants and about the configuration in general....
What is the right configuration?
Are there other constants that I have to set?
Is the PHYS_DRAM* the physical configuration or it is used for cache purpose?
What if I want an interleaved configuration?
Thank you in advance for your help,
Simone