AM389x - Memory map configuration

Hi Simone,

Simone Cilli1 said:

I think the right configuration could be:

#define PHYS_DRAM_1            0x80000000 /* DRAM Bank #1 */ 
#define PHYS_DRAM_1_SIZE 0x20000000 /* 512 MB */ 
#define PHYS_DRAM_2            0xA0000000 /* DRAM Bank #2 */ 
#define PHYS_DRAM_2_SIZE 0x20000000 /* 512 MB */
__raw_writel(0x0, DMM_LISA_MAP__0);
__raw_writel(0x0, DMM_LISA_MAP__1);
__raw_writel(0x80500100, DMM_LISA_MAP__2);
__raw_writel(0xA0500200, DMM_LISA_MAP__3);

This looks correct configuration for me. See also AM389x TRM, section 4.3.4 Address Management Using LISA Sections, and AM389x silicon errata, advisory 2.1.48.

You can also test your DDR with:

BR
Pavel

Hello Pavel!
Yes that configuration seems logic to me with respect of TI documentations.
Now I have several working configurations with and without interleaved on Sitara.

If that configuration is correct, my doubts come from the other my processors, a DM8168 and my old AM389X (version 2.0). Both are working with this config:
#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
#define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */
#define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */
#define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */
__raw_writel(0x0, DMM_LISA_MAP__0);
__raw_writel(0x0, DMM_LISA_MAP__1);
__raw_writel(0x80600100, DMM_LISA_MAP__2);
__raw_writel(0xC0600220, DMM_LISA_MAP__3);

How is it possible?
(My HW disable the most significan bit of the physical address, so 0x20... == 0x00...)
But, I don't have 2GB DDR, so I can't cover the memory from 0x80... to 0xFF....
From 0x80... to 0x9F... I have 512 MB. How does it know that it should skip to the next EMIF?

I found this phrase "On Media Controllers, the first address range is used to access DDR with cache enabled and the second address is used to access the same DDR with cache disabled." in processors.wiki.ti.com/.../EZSDK_Memory_Map.
Could it be the explanation? Could my memory be mapped 1GB cached and 1 GB no-cached to allow a "dual mode" access to the same area?

Thanks Pavel for your patience :)
Simone

I found the patch but not the LISA config.
The new configuration seems working. Great!
I'll test it today and tomorrow...

Where the 2 GB are managed in the DVRRDK code? I have the 03.50.00.05 version...

Thank you Pavel! You have a really deep knowledge on TI technologies!
Simone

Ps. The button "Answered" doesn't exist anymore on my browser. The button has the text "Verify Answer" now ;)

Simone Cilli1 said:

Where the 2 GB are managed in the DVRRDK code? I have the 03.50.00.05 version...

See if the below e2e threads will help:

BR
Pavel

Dear Pavel,

I'm a collegue of Simone. I think we already know.

thanks for your help.

We are having some different behaviour in some board with different silicon revision. (2.0 and 2.1). looking at the ref manual

on pag 2635 : revision history. I can see there there are several change on different frequency (DMM CLK from 380 to 364 Mhz , : Changed 48 MHz to 16 MHz for SYSCLK9 ... 432Mhz for Audio etc....). I'm going to check our uboot how is configuring, but just to know is there any patched rerfernce uboot that already take care of this important change on frequency... I wonder for example if the difference we are experiencing in DMM behaviour on different silicon revision could be due to 380Mhz clock...

Thanks

Omar Pighi

Omar,

Omar Pighi17 said:

We are having some different behaviour in some board with different silicon revision. (2.0 and 2.1)

The differences between 2.0 and 2.1 are described in the silicon errata document:

Omar Pighi17 said:

just to know is there any patched rerfernce uboot that already take care of this important change on frequency

See the below e2e thread:

See also the latest patches of the below u-boot branch:

BR
Pavel