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AM3358 GPMC_FCLK

Michi Yama
Guru 10030 points
Other Parts Discussed in Thread: AM3358

Hi,

I have one question regarding GPMC_FCLK changing.

I would like to change the frequency of GPMC_FCLK.

I  think GPMC_FCLK is 100MHz in ROM code. I would like to decrease the frequency of GPMC_FCLK to 50MHz, 25MHz, 10Mhz and so on.

Is it possible? If it is possible, please let me know how to do it.

I appreciate your quick reply.

Best regards,

Michi

  • 0
    TI__Guru**** 393215 points

    Hi,

    GPMC output clock can be changed by the GPMCFCLKDIVIDER bitfield of GPMC_CONFIG1_x Register. GPMC_FCLK itself cannot be changed. This is the CORE_CLKOUTM4 clock divided by 2, which is also used by other subsystems. All access-timing parameters can be multiplied by 2 by setting the GPMC_CONFIG1_x[4] TIMEPARAGRANULARITY bit. Increasing all access timing parameters allows support of slow devices.

  • 0 in reply to Biser Gatchev-XID
    Guru 10030 points
    Dear Biser-san,

    Thank you for your quick reply.

    > GPMC_FCLK itself cannot be changed.

    Do you mean GPMC_FCLK is fixed as 100MHz? Is it same other Sitara family processor?

    I appreciate your quick reply.

    Best regards,
    Michi
  • 0 in reply to Michi Yama
    TI__Guru**** 393215 points

    Michi Yama said:
    Do you mean GPMC_FCLK is fixed as 100MHz?

    Yes. If you want to change this clock you have to change the Core PLL frequency, and this will influence a large number of other clocks in the system, which are derived from the same PLL. See figure 8-10 in the AM335X TRM Rev. L.

    Michi Yama said:
    Is it same other Sitara family processor? 

    There are quite a lot of processors in the Sitara family. Please be more specific.

  • 0 in reply to Biser Gatchev-XID
    Guru 10030 points
    Dear Biser-san,

    Thank you for your support.

    I understood that GPMC_FCLK can change by changing the divider's value for making the CORE_CLKOUTM4. And its CLOCK changing will influence to other many clock, as you said.

    By the way, I have other question.
    According to the AM335x TRM, "DCAN_ocp_clk" also is made from CORE_CLKOUTM4. But the information of "DCAN_ocp_clk" is not written in TRM. From Figure 23-2 DCAN Block Diagram, I think that DCAN_ocp_clk is used for data transfer in AM335x. Is my understanding right?
    If it is so, I would like to know how influence is expected when CORE_CLKOUTM4's frequency is changed from 200MHz(normal setting) to 100MHz. Does DCAN peripheral have serious performance down?

    Please advise me.

    Best regards,
    Michi
  • 0 in reply to Michi Yama
    TI__Guru**** 393215 points
    DCAN_OCP_CLK is CORE_CLKOUTM4 /2 or 100MHz. This is the DCAN module interface clock to the L4 interconnect. Same reasoning applies here. It's highly undesirable to tweak these clocks.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 510 points

    Please let me know the GPMC_FCLK for AM57xx family.

    Thanks,

    Srinivas J

  • 0 in reply to Srinivas Jagarapu
    TI__Mastermind 26215 points
    Srinivas, this post started as AM3358....is your question regarding AM57x family? if so, perhaps it would make sense to start a new one...it would be easier for people searching for the same subject...