AM335x MDIO_CLK clock source

Daisuke Maeda

Guru 20205 points

What is the MDIO_CLK clock source? Is it the main_clk?

The division ratio for the frequency of MDIO_CLK is specified by the CLKDIV field in the MDIOCONTROL register, but the clock source is not clear.

Best regards,

Daisuke

0 Biser Gatchev-XID over 9 years ago

Yes, this is the main CPSW module logic/interface clock. This is the source clock for the MDIO divider.

0 Daisuke Maeda over 9 years ago in reply to Biser Gatchev-XID

Guru 20205 points

Hi Biser-san,

Thank you for your reply.

Best regards,

Daisuke

Processors forum