Hi,
I have one quesion regarding MDIO clock for gigabit ethernet switch.
According to the TRM of AM57xx, MD CLK frequency for Gigabit ethernet switch is defined by CLKDIV[15:0] bit of MDIO_CTRL register.
The formula is the below.
MDCLK frequency = ICLK frequency / (CLKDIV +1 )
I would like to confirm regarding "ICLK". I know there are two ICLKs. One is L3_ICLK(133MHz). And other is L4_ICLK(66.5MHz). Which ICLK do I use for MDIO_CTRL register?
Also, according to the 24.11.4.3.2.4 MDIO Clocking of TRM, there is the below sentence.
------
The MDIO clock is based on a divide-down of the interface (MAIN_CLK) clock, running at 125 MHz.The
application software or driver must control the divide-down value.
See the MDIO_CONTROL register for configuring the Clock Divider (CLKDIV) value.
------
From the above, I think that 125MHz clcok should be used for CLKDIV[15:0] MDIO_CTRL register.
Which clock should I use, L3_ICLK? L4_ICLK?, 125MHz?
Please advise me .
I appreciate your quick reply.
Best regards,
Michi
