AM335x problem reading ethernet phy registers

Geir Tore Olsen

Other Parts Discussed in Thread: TLK100, AM3352

I have a board with an AM3352 and two tlk100 phyceivers, and I use them as two seperate ethernet ports and it works. During boot I get:

[    2.175800] davinci_mdio 4a101000.mdio: phy[1]: device 4a101000.mdio:01, driver unknown
[    2.184295] davinci_mdio 4a101000.mdio: phy[2]: device 4a101000.mdio:02, driver unknown
[    3.510354] net eth0: initializing cpsw version 1.12 (0)
[    3.597318] net eth0: phy found : id is : 0x40005201
[    3.652298] net eth1: initializing cpsw version 1.12 (0)
[    3.737329] net eth1: phy found : id is : 0x40005201

"driver unknown" I think is that the PHYID is not recognized? However the generic phy driver should be used?

"id is : 0x40005201" is correct according to the datasheet.

However, when trying to read/write the phy registers I do not get any results (basically I only read back "1").

I have tried both mii-diag/mii-tool/ethtool.

When using ethtool -d eth0 raw off, the first line reads:

Offset          Values
------          ------
0x0000:         00 00 00 00 00 00 01 20 03 00 03 03 0c 00 00 00

I get values back, but the values does not seem correct. For instance the PHYID Reg 1 and two (address 0x02 and 0x03), do not match the values in the datasheet.

When running mii-tool

# ./mii-tool -vvv
SIOCGMIIREG on eth0 failed: Unknown error 524

registers for MII PHY 1:
    ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
    ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
    ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
    ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
product info: vendor ffffffff:ff:ff, model 63 rev 15
basic mode:   software reset, loopback, isolate, collision test, autonegotiation enabled
basic status: autonegotiation complete, remote fault, link ok
capabilities: 100baseT4 100baseTx-FD 100baseTx-HD 10baseT-FD 10baseT-HD flow-control
advertising: 100baseT4 100baseTx-FD 100baseTx-HD 10baseT-FD 10baseT-HD flow-control
link partner: 100baseT4 100baseTx-FD 100baseTx-HD 10baseT-FD 10baseT-HD flow-control

One other thing I notice is that MDIO_CLK (PIN M18) is active continous. From the configuration below, the clock is set to 1MHz and that is what I'm actually measuring.

From other projects where I have done with silmilar things, the clock is only active when actually reading and writing data to the phyceiver. But her it is always active?

When the kernel boots the phy id registers are read correctly. However from userspace I'm not able to talk to the phyceivers. I need this functionality to implement cable diagnostics for my project.

My device tree setup is as follows:

davinci_mdio: mdio@4a101000 {
               compatible = "ti,davinci_mdio";
               #address-cells = <1>;
               #size-cells = <0>;
               ti,hwmods = "davinci_mdio";
               bus_freq = <1000000>;
               reg = <0x4a101000 0x100>;
           };

    davinci_mdio_pins: pinmux_davinci_mdio_pins {
       pinctrl-single,pins = <
           /* MDIO */
           0x148 ( PIN_INPUT_PULLUP | MUX_MODE0 | SLEWCTRL_FAST ) /* mdio_data.mdio_data */
           0x14c ( PIN_OUTPUT_PULLUP | MUX_MODE0 ) /* mdio_clk.mdio_clk */
       >;
   };

   davinci_mdio_pins_sleep: pinmux_davinci_mdio_pins_sleep {
       pinctrl-single,pins = <
           /* MDIO reset value */
           0x148 ( PIN_INPUT_PULLDOWN | MUX_MODE7 )
           0x14c ( PIN_INPUT_PULLDOWN | MUX_MODE7 )
       >;
   };

&davinci_mdio {
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&davinci_mdio_pins>;
   pinctrl-1 = <&davinci_mdio_pins_sleep>;
   status = "okay";
};

I run linux kernel 3.14.

Best regards

Geir Tore Olsen

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Hi,

Don't you have a driver installed for the PHYs? I think this is the first thing to do. I will ask the software team to post what's the correct driver for TLK100.

0 Geir Tore Olsen over 9 years ago in reply to Biser Gatchev-XID

Prodigy 100 points

During boot, I get the following:

[ 2.163378] davinci_mdio 4a101000.mdio: detected phy mask fffffff9
[ 2.171569] libphy: 4a101000.mdio: probed
[ 2.175800] davinci_mdio 4a101000.mdio: phy[1]: device 4a101000.mdio:01, driver unknown
[ 2.184295] davinci_mdio 4a101000.mdio: phy[2]: device 4a101000.mdio:02, driver unknown
[ 3.597318] net eth0: phy found : id is : 0x40005201
[ 3.737329] net eth1: phy found : id is : 0x40005201
[ 5.597577] libphy: 4a101000.mdio:01 - Link is Up - 100/Full

As far as I can tell this means the the generic phy driver is used?

Best Regards
Geir Tore Olsen

0 Biser Gatchev-XID over 9 years ago in reply to Geir Tore Olsen

TI__Guru**** 393215 points

Is this kernel 3.14 from the TI Linux SDK?

0 Geir Tore Olsen over 9 years ago in reply to Biser Gatchev-XID

Prodigy 100 points

No I think this is 3.14 from kernel.org

Should that matter? I would think that the relevant patches for the kernel is in that as well?

Best Regards
Geir Tore Olsen

0 Biser Gatchev-XID over 9 years ago in reply to Geir Tore Olsen

TI__Guru**** 393215 points

I have forwarded this to the software team.

0 Yordan Kovachev over 9 years ago in reply to Geir Tore Olsen

TI__Guru**** 161600 points

Hi,

Geir Tore Olsen said:
As far as I can tell this means the the generic phy driver is used?

You are correct, this chip uses the generic phy driver.

However, I think the dts settings you post are not enough. Reference BBB or am335x-evm.dts files, you need &cpsw_emac0/1 and &mac dts nodes:

&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "mii";
};

&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "mii";
};

&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};

Also you need to mux the cpsw pins. Also can you attach your defconfig file, maybe you are missing some kernel setting.

Best Regards,
Yordan

0 Geir Tore Olsen over 9 years ago in reply to Yordan Kovachev

Prodigy 100 points

Hi There!

As I said earlier the kernel itself is able to read the phy id correctly, it is only from use space I'm unable to talk to the phyceivers.

My complete device tree setup for ethernet is as follows:

Fullscreen dts.txt Download

mii_pins: pinmux_mii_pins {
 pinctrl-single,pins = <
 0x108 ( PIN_INPUT_PULLDOWN | MUX_MODE0 ) /* (H16) gmii1_col.gmii1_col */
 0x10c ( PIN_INPUT | MUX_MODE0 ) /* (H17) gmii1_crs.gmii1_crs */
 0x110 ( PIN_INPUT | MUX_MODE0 ) /* (J15) gmii1_rxer.gmii1_rxer */
 0x114 ( PIN_OUTPUT | MUX_MODE0 ) /* (J16) gmii1_txen.gmii1_txen */
 0x118 ( PIN_INPUT | MUX_MODE0 ) /* (J17) gmii1_rxdv.gmii1_rxdv */
 0x12c ( PIN_INPUT | MUX_MODE0 ) /* (K18) gmii1_txclk.gmii1_txclk */
 0x130 ( PIN_INPUT | MUX_MODE0 ) /* (L18) gmii1_rxclk.gmii1_rxclk */
 0x128 ( PIN_OUTPUT | MUX_MODE0 ) /* (K17) gmii1_txd0.gmii1_txd0 */
 0x124 ( PIN_OUTPUT | MUX_MODE0 ) /* (K16) gmii1_txd1.gmii1_txd1 */
 0x120 ( PIN_OUTPUT | MUX_MODE0 ) /* (K15) gmii1_txd2.gmii1_txd2 */
 0x11c ( PIN_OUTPUT | MUX_MODE0 ) /* (J18) gmii1_txd3.gmii1_txd3 */
 0x140 ( PIN_INPUT | MUX_MODE0 ) /* (M16) gmii1_rxd0.gmii1_rxd0 */
 0x13c ( PIN_INPUT | MUX_MODE0 ) /* (L15) gmii1_rxd1.gmii1_rxd1 */
 0x138 ( PIN_INPUT | MUX_MODE0 ) /* (L16) gmii1_rxd2.gmii1_rxd2 */
 0x134 ( PIN_INPUT | MUX_MODE0 ) /* (L17) gmii1_rxd3.gmii1_rxd3 */

 0x78 ( PIN_INPUT_PULLDOWN | MUX_MODE1 ) /* (U18) gpmc_be1n.gmii2_col */
 0x70 ( PIN_INPUT | MUX_MODE1 ) /* (T17) gpmc_wait0.gmii2_crs */
 0x74 ( PIN_INPUT | MUX_MODE1 ) /* (U17) gpmc_wpn.gmii2_rxer */
 0x40 ( PIN_OUTPUT | MUX_MODE1 ) /* (R13) gpmc_a0.gmii2_txen */
 0x44 ( PIN_INPUT | MUX_MODE1 ) /* (V14) gpmc_a1.gmii2_rxdv */
 0x58 ( PIN_INPUT | MUX_MODE1 ) /* (U15) gpmc_a6.gmii2_txclk */
 0x5c ( PIN_INPUT | MUX_MODE1 ) /* (T15) gpmc_a7.gmii2_rxclk */
 0x54 ( PIN_OUTPUT | MUX_MODE1 ) /* (V15) gpmc_a5.gmii2_txd0 */
 0x50 ( PIN_OUTPUT | MUX_MODE1 ) /* (R14) gpmc_a4.gmii2_txd1 */
 0x4c ( PIN_OUTPUT | MUX_MODE1 ) /* (T14) gpmc_a3.gmii2_txd2 */
 0x48 ( PIN_OUTPUT | MUX_MODE1 ) /* (U14) gpmc_a2.gmii2_txd3 */
 0x6c ( PIN_INPUT | MUX_MODE1 ) /* (V17) gpmc_a11.gmii2_rxd0 */
 0x68 ( PIN_INPUT | MUX_MODE1 ) /* (T16) gpmc_a10.gmii2_rxd1 */
 0x64 ( PIN_INPUT | MUX_MODE1 ) /* (U16) gpmc_a9.gmii2_rxd2 */
 0x60 ( PIN_INPUT | MUX_MODE1 ) /* (V16) gpmc_a8.gmii2_rxd3 */
 >;
 };

 mii_pins_sleep: pinmux_mii_pins_sleep {
 pinctrl-single,pins = <
 0x108 ( PIN_INPUT_PULLDOWN | MUX_MODE0 ) /* (H16) gmii1_col.gmii1_col */
 0x10c ( PIN_INPUT_PULLDOWN | MUX_MODE0 ) /* (H17) gmii1_crs.gmii1_crs */
 0x110 ( PIN_INPUT_PULLDOWN | MUX_MODE0 ) /* (J15) gmii1_rxer.gmii1_rxer */
 0x114 ( PIN_OUTPUT_PULLDOWN | MUX_MODE0 ) /* (J16) gmii1_txen.gmii1_txen */
 0x118 ( PIN_INPUT_PULLDOWN | MUX_MODE0 ) /* (J17) gmii1_rxdv.gmii1_rxdv */
 0x12c ( PIN_INPUT_PULLDOWN | MUX_MODE0 ) /* (K18) gmii1_txclk.gmii1_txclk */
 0x130 ( PIN_INPUT_PULLDOWN | MUX_MODE0 ) /* (L18) gmii1_rxclk.gmii1_rxclk */
 0x128 ( PIN_OUTPUT_PULLDOWN | MUX_MODE0 ) /* (K17) gmii1_txd0.gmii1_txd0 */
 0x124 ( PIN_OUTPUT_PULLDOWN | MUX_MODE0 ) /* (K16) gmii1_txd1.gmii1_txd1 */
 0x120 ( PIN_OUTPUT_PULLDOWN | MUX_MODE0 ) /* (K15) gmii1_txd2.gmii1_txd2 */
 0x11c ( PIN_OUTPUT_PULLDOWN | MUX_MODE0 ) /* (J18) gmii1_txd3.gmii1_txd3 */
 0x140 ( PIN_INPUT_PULLDOWN | MUX_MODE0 ) /* (M16) gmii1_rxd0.gmii1_rxd0 */
 0x13c ( PIN_INPUT_PULLDOWN | MUX_MODE0 ) /* (L15) gmii1_rxd1.gmii1_rxd1 */
 0x138 ( PIN_INPUT_PULLDOWN | MUX_MODE0 ) /* (L16) gmii1_rxd2.gmii1_rxd2 */
 0x134 ( PIN_INPUT_PULLDOWN | MUX_MODE0 ) /* (L17) gmii1_rxd3.gmii1_rxd3 */

 0x78 ( PIN_INPUT_PULLDOWN | MUX_MODE1 ) /* (U18) gpmc_be1n.gmii2_col */
 0x70 ( PIN_INPUT_PULLDOWN | MUX_MODE1 ) /* (T17) gpmc_wait0.gmii2_crs */
 0x74 ( PIN_INPUT_PULLDOWN | MUX_MODE1 ) /* (U17) gpmc_wpn.gmii2_rxer */
 0x40 ( PIN_OUTPUT_PULLDOWN | MUX_MODE1 ) /* (R13) gpmc_a0.gmii2_txen */
 0x44 ( PIN_INPUT_PULLDOWN | MUX_MODE1 ) /* (V14) gpmc_a1.gmii2_rxdv */
 0x58 ( PIN_INPUT_PULLDOWN | MUX_MODE1 ) /* (U15) gpmc_a6.gmii2_txclk */
 0x5c ( PIN_INPUT_PULLDOWN | MUX_MODE1 ) /* (T15) gpmc_a7.gmii2_rxclk */
 0x54 ( PIN_OUTPUT_PULLDOWN | MUX_MODE1 ) /* (V15) gpmc_a5.gmii2_txd0 */
 0x50 ( PIN_OUTPUT_PULLDOWN | MUX_MODE1 ) /* (R14) gpmc_a4.gmii2_txd1 */
 0x4c ( PIN_OUTPUT_PULLDOWN | MUX_MODE1 ) /* (T14) gpmc_a3.gmii2_txd2 */
 0x48 ( PIN_OUTPUT_PULLDOWN | MUX_MODE1 ) /* (U14) gpmc_a2.gmii2_txd3 */
 0x6c ( PIN_INPUT_PULLDOWN | MUX_MODE1 ) /* (V17) gpmc_a11.gmii2_rxd0 */
 0x68 ( PIN_INPUT_PULLDOWN | MUX_MODE1 ) /* (T16) gpmc_a10.gmii2_rxd1 */
 0x64 ( PIN_INPUT_PULLDOWN | MUX_MODE1 ) /* (U16) gpmc_a9.gmii2_rxd2 */
 0x60 ( PIN_INPUT_PULLDOWN | MUX_MODE1 ) /* (V16) gpmc_a8.gmii2_rxd3 */
 >;
 };

 davinci_mdio_pins: pinmux_davinci_mdio_pins {
 pinctrl-single,pins = <
 /* MDIO */
 0x148 ( PIN_INPUT_PULLUP | MUX_MODE0 | SLEWCTRL_FAST ) /* mdio_data.mdio_data */
 0x14c ( PIN_OUTPUT_PULLUP | MUX_MODE0 ) /* mdio_clk.mdio_clk */
 >;
 };

 davinci_mdio_pins_sleep: pinmux_davinci_mdio_pins_sleep {
 pinctrl-single,pins = <
 /* MDIO reset value */
 0x148 ( PIN_INPUT_PULLDOWN | MUX_MODE7 )
 0x14c ( PIN_INPUT_PULLDOWN | MUX_MODE7 )
 >;
};

 &davinci_mdio {
 pinctrl-names = "default", "sleep";
 pinctrl-0 = <&davinci_mdio_pins>;
 pinctrl-1 = <&davinci_mdio_pins_sleep>;
 status = "okay";
 };

 &cpsw_emac0 {
 phy_id = <&davinci_mdio>, <1>;
 phy-mode = "mii";
 dual_emac_res_vlan = <1>;
 };

 &cpsw_emac1 {
 phy_id = <&davinci_mdio>, <2>;
 phy-mode = "mii";
 dual_emac_res_vlan = <2>;
 };

 &mac {
 pinctrl-names = "default", "sleep";
 pinctrl-0 = <&mii_pins>;
 pinctrl-1 = <&mii_pins_sleep>;
 status = "okay";
 dual_emac = <1>;
 };

And my kernel configuration is as follows: kkonfig.txt

0 Geir Tore Olsen over 9 years ago in reply to Geir Tore Olsen

Prodigy 100 points

Any progress on this?

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AM335x problem reading ethernet phy registers