Hello to all! I'm new in 6467t dsp. I need just to generate pattern image in NTSC, then send to ADV7393. I have error with this. Can anybody help?
SYS_PINMUX0 = 0 | ( 0 << 31 ) // VBUSDIS [USB_DRVVBUS] | ( 0 << 30 ) // STCCK [GPIO4] | ( 0 << 29 ) // AUDCK1 [GPIO2] | ( 0 << 28 ) // AUDCK0 [GPIO3] | ( 0 << 24 ) // [2]CRGMUX [no CRGEN] | ( 0 << 22 ) // [2]TSSOMUX [VP_DOUT[11:8]] | ( 0 << 20 ) // [2]TSSIMUX [VP_DIN[7:0]] | ( 0 << 18 ) // [2]PTSOMUX [VP_DIN[7:0]] | ( 0 << 16 ) // [2]PTSIMUX [VP_DIN[15:8]] | ( 0 << 5 ) // PINTD [GPIO5] | ( 0 << 2 ) // PCIEN [no PCI] | ( 0 << 1 ) // HPIEN [no HPI] | ( 1 << 0 ); // ATAEN [ATA/NAND] /* Video Clocks */ SYS_VIDCLKCTL = 0 | ( 4 << 12 ) // Video Chnl 3 Clock [VP_CLKIN0] // VID_CLK_B | ( 4 << 8 ) // Video Chnl 2 Clock [VP_CLKIN0] // VID_CLK_A | ( 1 << 4 ); // Video Chnl 1 Clock [VP_CLKIN1] /* VS Clock Disable */ SYS_VSCLKDIS = 0 | ( 0 << 11 ) // VPIF Ch 3 [Enable] | ( 0 << 10 ) // VPIF Ch 2 [Enable] | ( 0 << 9 ) // VPIF Ch 1 [Enable] | ( 0 << 8 ) // VPIF Ch 0 [Enable] | ( 1 << 7 ) // TSIF1 Count [Disable] | ( 1 << 6 ) // TSIF0 Count [Disable] | ( 1 << 5 ) // TSIF1 TX Clk [Disable] | ( 1 << 4 ) // TSIF0 TX Clk [Disable] | ( 1 << 3 ) // TSIF1 RX Clk [Disable] | ( 1 << 2 ) // TSIF0 RX Clk [Disable] | ( 1 << 1 ) // CRG 1 Enable [Disable] | ( 1 << 0 ); // CRG 0 Enable [Disable]
Configuration of ADV7393:
//8-bit 525i YCbCr In(EAV/SAV), CVBS/Y-C Out //Software reset errors = adv7393_rset(0x17, 0x02); //All DACs enabled. PLL enabled (16x). errors = adv7393_rget(0x00, ®); errors = adv7393_rset(0x00, 0x1c); //SD input mode errors = adv7393_rget(0x01, ®); errors = adv7393_rset(0x01, reg | 0x00); //NTSC. SSAF luma filter. 1.3 MHz chroma filter. errors = adv7393_rget(0x80, ®); errors = adv7393_rset(0x80, reg | 0x10); //Pixel data valid. RGB out. SSAF PrPb filer. Active video edge control. errors = adv7393_rget(0x82, ®); errors = adv7393_rset(0x82, reg | 0xcb);