Detail DDR3 software leveling procedure for AM5728 customized board

Yicheng Bai

Other Parts Discussed in Thread: AM5728

Hi,

I am now trying to debug my customized AM5728 board. I am worried about the DDR3 layout and routing results. Since we do not have the emulator and CCS for hardware leveling. I am thinking about doing the software leveling for my board. Does anyone have detail instructions or procedure for doing that? I am new for this type of hardware debugging. Please help me with this............ :)

Thanks, Yicheng

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Hi,

Software leveling is not supported on AM57X.

0 Yicheng Bai over 9 years ago in reply to Biser Gatchev-XID

Intellectual 600 points

Hi Biser,

Thank you so much for your quick reply. I really did not expect to get the answer this fast. For the hardware leveling, would you please send me the detailed instruction/procedure? What are actually needed for that in addition to the emulator and CCS.

Thanks, Yicheng

0 Biser Gatchev-XID over 9 years ago in reply to Yicheng Bai

TI__Guru**** 393215 points

There is no procedure for hardware leveling. This is done at run-time by the EMIF hardware.

0 Yicheng Bai over 9 years ago in reply to Biser Gatchev-XID

Intellectual 600 points

I am a little confused here. Does this mean that for AM5728 we do not need to do the DDR3 leveling for the new designs? If we still need to do that, would you please tell me what are the options?

Best,
Yicheng

0 Biser Gatchev-XID over 9 years ago in reply to Yicheng Bai

TI__Guru**** 393215 points

If you mean a similar procedure to the one that is necessary for AM335X: processors.wiki.ti.com/.../AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling
This is not necessary on AM437X and AM57X.

0 Yicheng Bai over 9 years ago in reply to Biser Gatchev-XID

Intellectual 600 points

Thank you so much for this information. i really appreciate that. Actually the link you sent is what I am trying to find that could be used on AM57xx board. That means that AM57xx has already embedded this kind of procedure with in the u-boot or kernel codes. Please correct me if i am wrong at this point.

Best, Yicheng

0 Biser Gatchev-XID over 9 years ago in reply to Yicheng Bai

TI__Guru**** 393215 points

No, this does not involve software at all. It's done by the AM57X Memory controller hardware. In software you only need to set proper memory timings and memory map.

0 Yicheng Bai over 9 years ago in reply to Biser Gatchev-XID

Intellectual 600 points

For the memory timings and memory map configuration, would you please share with me some example instructions or something like that?

Thanks, Yicheng

0 Biser Gatchev-XID over 9 years ago in reply to Yicheng Bai

TI__Guru**** 393215 points

I have asked the software team, I'm not a software expert myself.

0 Yicheng Bai over 9 years ago in reply to Biser Gatchev-XID

Intellectual 600 points

That is great. Thank you so much for your help.

Best, yicheng

0 Yordan Kovachev over 9 years ago in reply to Yicheng Bai

TI__Guru**** 161600 points

Hi,

You can use the AM572x GEL files for reference (it comes with the CCS installation). I am attaching the relevant DDR Config part:

Fullscreen DDR_Config.txt Download

#define uint32_t                unsigned int
#define WR_MEM_32(addr, data)   *(uint32_t*)(addr) =(uint32_t)(data)
#define RD_MEM_32(addr)         *(uint32_t*)(addr)
#define EMIF1_BASE_ADDR         (0x4C000000)
#define EMIF2_BASE_ADDR         (0x4D000000)

#define DEBUG_PRINT             (1)
#define HW_LEVELING_ENABLED     (1) 

menuitem "DDR Memory config"

uint32_t i;
uint32_t SDRAM_TIM_1;
uint32_t SDRAM_TIM_2;
uint32_t SDRAM_TIM_3;
uint32_t LPDDR2_NVM_TIM;
uint32_t PWR_MGMT_CTRL;
uint32_t OCP_CONFIG;
uint32_t IODFT_TLGC;
uint32_t DLL_CALIB_CTRL;
uint32_t ZQ_CONFIG;
uint32_t TEMP_ALERT_CONFIG;
uint32_t RDWR_LVL_RMP_WIN;
uint32_t RDWR_LVL_RMP_CTRL;
uint32_t DDR_PHY_CTRL_1;
uint32_t DDR_PHY_CTRL_2;
uint32_t PRI_COS_MAP;
uint32_t CONNID_COS_1_MAP;
uint32_t CONNID_COS_2_MAP;
uint32_t RD_WR_EXEC_THRSH;
uint32_t COS_CONFIG;
uint32_t EXT_PHY_CTRL_2;
uint32_t EXT_PHY_CTRL_3;
uint32_t EXT_PHY_CTRL_4;
uint32_t EXT_PHY_CTRL_5;
uint32_t EXT_PHY_CTRL_6;
uint32_t EXT_PHY_CTRL_7;
uint32_t EXT_PHY_CTRL_8;
uint32_t EXT_PHY_CTRL_9;
uint32_t EXT_PHY_CTRL_10;
uint32_t EXT_PHY_CTRL_11;
uint32_t EXT_PHY_CTRL_12;
uint32_t EXT_PHY_CTRL_13;
uint32_t EXT_PHY_CTRL_14;
uint32_t EXT_PHY_CTRL_15;
uint32_t EXT_PHY_CTRL_16;
uint32_t EXT_PHY_CTRL_17;
uint32_t EXT_PHY_CTRL_18;
uint32_t EXT_PHY_CTRL_19;
uint32_t EXT_PHY_CTRL_20;
uint32_t EXT_PHY_CTRL_21;
uint32_t EXT_PHY_CTRL_22;
uint32_t EXT_PHY_CTRL_23;
uint32_t EXT_PHY_CTRL_24;
uint32_t EXT_PHY_CTRL_25;
uint32_t EXT_PHY_CTRL_26;
uint32_t EXT_PHY_CTRL_27;
uint32_t EXT_PHY_CTRL_28;
uint32_t EXT_PHY_CTRL_29;
uint32_t EXT_PHY_CTRL_30;
uint32_t EXT_PHY_CTRL_31;
uint32_t EXT_PHY_CTRL_32;
uint32_t EXT_PHY_CTRL_33;
uint32_t EXT_PHY_CTRL_34;
uint32_t EXT_PHY_CTRL_35;
uint32_t EXT_PHY_CTRL_36;
uint32_t SDRAM_REF_CTRL;
uint32_t SDRAM_CONFIG_2;
uint32_t SDRAM_CONFIG;

reset_emif_params_ddr3_532()
{
    SDRAM_TIM_1        = 0xCEEF266B;
    SDRAM_TIM_2        = 0x328F7FDA;
    SDRAM_TIM_3        = 0x027F88A8;
    LPDDR2_NVM_TIM     = 0x00000000;
    PWR_MGMT_CTRL      = 0x00000000;
    OCP_CONFIG         = 0x0A500000;
    IODFT_TLGC         = 0x00002011;
    DLL_CALIB_CTRL     = 0x00050000;
    ZQ_CONFIG          = 0x5007190B;
    TEMP_ALERT_CONFIG  = 0x00000000;
    RDWR_LVL_RMP_WIN   = 0x00000000;

    if(HW_LEVELING_ENABLED)
    {
        RDWR_LVL_RMP_CTRL  = 0x80000000;
        DDR_PHY_CTRL_1     = 0x0024400C;
    }
    else
    {
        RDWR_LVL_RMP_CTRL  = 0x00000000;
        DDR_PHY_CTRL_1     = 0x0E24400C;
    }

    DDR_PHY_CTRL_2     = 0x00000000;
    PRI_COS_MAP        = 0x00000000;
    CONNID_COS_1_MAP   = 0x00000000;
    CONNID_COS_2_MAP   = 0x00000000;
    RD_WR_EXEC_THRSH   = 0x00000305;
    COS_CONFIG         = 0x00FFFFFF;

    //GATE
    EXT_PHY_CTRL_2     = 0x00BB00BB;
    EXT_PHY_CTRL_3     = 0x00BB00BB;
    EXT_PHY_CTRL_4     = 0x00BB00BB;
    EXT_PHY_CTRL_5     = 0x00BB00BB;
    EXT_PHY_CTRL_6     = 0x00BB00BB;

    //RD_DQS
    EXT_PHY_CTRL_7     = 0x00440044;
    EXT_PHY_CTRL_8     = 0x00440044;
    EXT_PHY_CTRL_9     = 0x00440044;
    EXT_PHY_CTRL_10    = 0x00440044;
    EXT_PHY_CTRL_11    = 0x00440044;

    //WR_DATA
    EXT_PHY_CTRL_12    = 0x007F007F;
    EXT_PHY_CTRL_13    = 0x007F007F;
    EXT_PHY_CTRL_14    = 0x007F007F;
    EXT_PHY_CTRL_15    = 0x007F007F;
    EXT_PHY_CTRL_16    = 0x007F007F;

    //WR_DQS
    EXT_PHY_CTRL_17    = 0x00600060;
    EXT_PHY_CTRL_18    = 0x00600060;
    EXT_PHY_CTRL_19    = 0x00600060;
    EXT_PHY_CTRL_20    = 0x00600060;
    EXT_PHY_CTRL_21    = 0x00600060;

    EXT_PHY_CTRL_22    = 0x00000000;
    EXT_PHY_CTRL_23    = 0x00600020;
    EXT_PHY_CTRL_24    = 0x40010080;
    EXT_PHY_CTRL_25    = (0x40|(0x40<<7)|(0x40<<14)|(0x40<<21));//0x08102040;

    //Inputting Init values for HW levelling with seed values 
    EXT_PHY_CTRL_26    = ((0x40<<16)|(0x40<<0));
    EXT_PHY_CTRL_27    = ((0x40<<16)|(0x40<<0));
    EXT_PHY_CTRL_28    = ((0x40<<16)|(0x40<<0));
    EXT_PHY_CTRL_29    = ((0x40<<16)|(0x40<<0));
    EXT_PHY_CTRL_30    = ((0x40<<16)|(0x40<<0));
    EXT_PHY_CTRL_31    = 0x00000000;
    EXT_PHY_CTRL_32    = 0x00000000;
    EXT_PHY_CTRL_33    = 0x00000000;
    EXT_PHY_CTRL_34    = 0x00000000;
    EXT_PHY_CTRL_35    = 0x00000000;

    //Using the max value of DQ samples for HW levelling  
    EXT_PHY_CTRL_36    = ((0xF<<4)|(0xF<<0));

    SDRAM_REF_CTRL     = 0x00001035;
    SDRAM_CONFIG_2     = 0x00000000;
    SDRAM_CONFIG       = 0x61851B32;
}


set_emif1_params_ddr3_532()
{
    SDRAM_TIM_1        = 0xCEEF266B;
    SDRAM_TIM_2        = 0x328F7FDA;
    SDRAM_TIM_3        = 0x027F88A8;
    ZQ_CONFIG          = 0x0007190B;
    if(HW_LEVELING_ENABLED)
    {
        RDWR_LVL_RMP_CTRL  = 0x80000000;
        DDR_PHY_CTRL_1     = 0x0024400A;
    }
    else
    {
        RDWR_LVL_RMP_CTRL  = 0x00000000;
        DDR_PHY_CTRL_1     = 0x0E24400A;
    }
    SDRAM_REF_CTRL     = 0x00001035;
    SDRAM_CONFIG       = 0x61851B32; 
}

set_emif2_params_ddr3_532()
{
    SDRAM_TIM_1        = 0xCEEF266B;
    SDRAM_TIM_2        = 0x328F7FDA;
    SDRAM_TIM_3        = 0x027F88A8;
    ZQ_CONFIG          = 0x0007190B;
    if(HW_LEVELING_ENABLED)
    {
        RDWR_LVL_RMP_CTRL  = 0x80000000;
        DDR_PHY_CTRL_1     = 0x0024400A;
    }
    else
    {
        RDWR_LVL_RMP_CTRL  = 0x00000000;
        DDR_PHY_CTRL_1     = 0x0E24400A;
    }
    SDRAM_REF_CTRL     = 0x00001035;
    SDRAM_CONFIG       = 0x61851B32; 
}


EMIF_Config(uint32_t base_addr)
{
    uint32_t loop_cnt;

    WR_MEM_32(base_addr + 0x000000E4, DDR_PHY_CTRL_1);
    WR_MEM_32(base_addr + 0x000000E8, DDR_PHY_CTRL_1);    
    if(DDR_PHY_CTRL_1 & 0x00040000)
    {
       WR_MEM_32(base_addr + 0x00000200, ((0x100<<20)|(0x100<<10)|(0x100<<0))); //EXT_PHY_CTRL_1 --
       WR_MEM_32(base_addr + 0x00000204, ((0x100<<20)|(0x100<<10)|(0x100<<0))); //EXT_PHY_CTRL_1_SHDW --
    }
    else
    {
       WR_MEM_32(base_addr + 0x00000200, ((0x80<<20)|(0x80<<10)|(0x80<<0))); //EXT_PHY_CTRL_1 --
       WR_MEM_32(base_addr + 0x00000204, ((0x80<<20)|(0x80<<10)|(0x80<<0))); //EXT_PHY_CTRL_1_SHDW --
    }    
    
    //Force Slave ratio values not required if HW levelling is enabled
    if (!HW_LEVELING_ENABLED)
    {
       //Force ratio values for Gate
       WR_MEM_32(base_addr + 0x00000208, EXT_PHY_CTRL_2);
       WR_MEM_32(base_addr + 0x0000020C, EXT_PHY_CTRL_2);
       WR_MEM_32(base_addr + 0x00000210, EXT_PHY_CTRL_3);
       WR_MEM_32(base_addr + 0x00000214, EXT_PHY_CTRL_3);
       WR_MEM_32(base_addr + 0x00000218, EXT_PHY_CTRL_4);
       WR_MEM_32(base_addr + 0x0000021C, EXT_PHY_CTRL_4);
       WR_MEM_32(base_addr + 0x00000220, EXT_PHY_CTRL_5);
       WR_MEM_32(base_addr + 0x00000224, EXT_PHY_CTRL_5);
       WR_MEM_32(base_addr + 0x00000228, EXT_PHY_CTRL_6);
       WR_MEM_32(base_addr + 0x0000022C, EXT_PHY_CTRL_6);
     
       //Force ratio values for RD_DQS
       WR_MEM_32(base_addr + 0x00000230, EXT_PHY_CTRL_7);
       WR_MEM_32(base_addr + 0x00000234, EXT_PHY_CTRL_7);
       WR_MEM_32(base_addr + 0x00000238, EXT_PHY_CTRL_8);
       WR_MEM_32(base_addr + 0x0000023C, EXT_PHY_CTRL_8);
       WR_MEM_32(base_addr + 0x00000240, EXT_PHY_CTRL_9);
       WR_MEM_32(base_addr + 0x00000244, EXT_PHY_CTRL_9);
       WR_MEM_32(base_addr + 0x00000248, EXT_PHY_CTRL_10);
       WR_MEM_32(base_addr + 0x0000024C, EXT_PHY_CTRL_10);
       WR_MEM_32(base_addr + 0x00000250, EXT_PHY_CTRL_11);
       WR_MEM_32(base_addr + 0x00000254, EXT_PHY_CTRL_11);
     
       //Force ratio values for WR_DQ
       WR_MEM_32(base_addr + 0x00000258, EXT_PHY_CTRL_12);
       WR_MEM_32(base_addr + 0x0000025C, EXT_PHY_CTRL_12);
       WR_MEM_32(base_addr + 0x00000260, EXT_PHY_CTRL_13);
       WR_MEM_32(base_addr + 0x00000264, EXT_PHY_CTRL_13);
       WR_MEM_32(base_addr + 0x00000268, EXT_PHY_CTRL_14);
       WR_MEM_32(base_addr + 0x0000026C, EXT_PHY_CTRL_14);
       WR_MEM_32(base_addr + 0x00000270, EXT_PHY_CTRL_15);
       WR_MEM_32(base_addr + 0x00000274, EXT_PHY_CTRL_15);
       WR_MEM_32(base_addr + 0x00000278, EXT_PHY_CTRL_16);
       WR_MEM_32(base_addr + 0x0000027C, EXT_PHY_CTRL_16);
     
       //Force ratio values for WR_DQS
       WR_MEM_32(base_addr + 0x00000280, EXT_PHY_CTRL_17);
       WR_MEM_32(base_addr + 0x00000284, EXT_PHY_CTRL_17);
       WR_MEM_32(base_addr + 0x00000288, EXT_PHY_CTRL_18);
       WR_MEM_32(base_addr + 0x0000028C, EXT_PHY_CTRL_18);
       WR_MEM_32(base_addr + 0x00000290, EXT_PHY_CTRL_19);
       WR_MEM_32(base_addr + 0x00000294, EXT_PHY_CTRL_19);
       WR_MEM_32(base_addr + 0x00000298, EXT_PHY_CTRL_20);
       WR_MEM_32(base_addr + 0x0000029C, EXT_PHY_CTRL_20);
       WR_MEM_32(base_addr + 0x000002A0, EXT_PHY_CTRL_21);
       WR_MEM_32(base_addr + 0x000002A4, EXT_PHY_CTRL_21);
    }
    else 
    {
        // Use Init values if HW leveling is enabled        
        // Gate level Init ratios
        WR_MEM_32(base_addr + 0x000002C8, EXT_PHY_CTRL_26);
        WR_MEM_32(base_addr + 0x000002CC, EXT_PHY_CTRL_26);
        WR_MEM_32(base_addr + 0x000002D0, EXT_PHY_CTRL_27);
        WR_MEM_32(base_addr + 0x000002D4, EXT_PHY_CTRL_27);
        WR_MEM_32(base_addr + 0x000002D8, EXT_PHY_CTRL_28);
        WR_MEM_32(base_addr + 0x000002DC, EXT_PHY_CTRL_28);
        WR_MEM_32(base_addr + 0x000002E0, EXT_PHY_CTRL_29);
        WR_MEM_32(base_addr + 0x000002E4, EXT_PHY_CTRL_29);
        WR_MEM_32(base_addr + 0x000002E8, EXT_PHY_CTRL_30);
        WR_MEM_32(base_addr + 0x000002EC, EXT_PHY_CTRL_30);
        
        // WR DQS Init ratios
        WR_MEM_32(base_addr + 0x000002F0, EXT_PHY_CTRL_31);
        WR_MEM_32(base_addr + 0x000002F4, EXT_PHY_CTRL_31);
        WR_MEM_32(base_addr + 0x000002F8, EXT_PHY_CTRL_32);
        WR_MEM_32(base_addr + 0x000002FC, EXT_PHY_CTRL_32);
        WR_MEM_32(base_addr + 0x00000300, EXT_PHY_CTRL_33);
        WR_MEM_32(base_addr + 0x00000304, EXT_PHY_CTRL_33);
        WR_MEM_32(base_addr + 0x00000308, EXT_PHY_CTRL_34);
        WR_MEM_32(base_addr + 0x0000030C, EXT_PHY_CTRL_34);
        WR_MEM_32(base_addr + 0x00000310, EXT_PHY_CTRL_35);
        WR_MEM_32(base_addr + 0x00000314, EXT_PHY_CTRL_35);     
    }
    
    // PHY settings for DQ offset, DLL override delay, levelling etc.
    WR_MEM_32(base_addr + 0x000002A8, EXT_PHY_CTRL_22);
    WR_MEM_32(base_addr + 0x000002AC, EXT_PHY_CTRL_22);
    WR_MEM_32(base_addr + 0x000002B0, EXT_PHY_CTRL_23);
    WR_MEM_32(base_addr + 0x000002B4, EXT_PHY_CTRL_23);
    WR_MEM_32(base_addr + 0x000002B8, EXT_PHY_CTRL_24);
    WR_MEM_32(base_addr + 0x000002BC, EXT_PHY_CTRL_24);
    WR_MEM_32(base_addr + 0x000002C0, EXT_PHY_CTRL_25);
    WR_MEM_32(base_addr + 0x000002C4, EXT_PHY_CTRL_25);
    WR_MEM_32(base_addr + 0x00000318, EXT_PHY_CTRL_36);
    WR_MEM_32(base_addr + 0x0000031C, EXT_PHY_CTRL_36);
    
    //Apply PHY RESET to latch all the PHY registers
    WR_MEM_32(base_addr + 0x00000060, 0x00002011);
    WR_MEM_32(base_addr + 0x00000060, 0x00002411);
    WR_MEM_32(base_addr + 0x00000060, 0x00002011);
    
    // Disable initialization and refreshes until the EMIF is programmed
    WR_MEM_32(base_addr + 0x00000010, 0x80003000);
    WR_MEM_32(base_addr + 0x00000014, 0x80003000);
       
    //Set up the EMIF registers
    WR_MEM_32(base_addr + 0x00000018, SDRAM_TIM_1);
    WR_MEM_32(base_addr + 0x0000001C, SDRAM_TIM_1);
    WR_MEM_32(base_addr + 0x00000020, SDRAM_TIM_2);
    WR_MEM_32(base_addr + 0x00000024, SDRAM_TIM_2);
    WR_MEM_32(base_addr + 0x00000028, SDRAM_TIM_3);
    WR_MEM_32(base_addr + 0x0000002C, SDRAM_TIM_3);
   
    WR_MEM_32(base_addr + 0x00000038, PWR_MGMT_CTRL);
    WR_MEM_32(base_addr + 0x0000003C, PWR_MGMT_CTRL);
    // Leave these as RESET values; 
    WR_MEM_32(base_addr + 0x00000060, IODFT_TLGC);    
    WR_MEM_32(base_addr + 0x000000C8, ZQ_CONFIG);
    WR_MEM_32(base_addr + 0x000000D4, RDWR_LVL_RMP_WIN);
    WR_MEM_32(base_addr + 0x000000D8, RDWR_LVL_RMP_CTRL);
    WR_MEM_32(base_addr + 0x000000DC, 0x00000000);   
  
    //Set up long refresh time so that RESET-CKE timing is met
    WR_MEM_32(base_addr + 0x00000014, 0x3000);
    WR_MEM_32(base_addr + 0x00000010, 0x3000);
    WR_MEM_32(base_addr + 0x0000000C, SDRAM_CONFIG_2);
    WR_MEM_32(base_addr + 0x00000008, SDRAM_CONFIG);
    //Now update with the correct refresh time
    WR_MEM_32(base_addr + 0x00000014, SDRAM_REF_CTRL);
    WR_MEM_32(base_addr + 0x00000010, SDRAM_REF_CTRL);
    
    //Delay till the initialization is complete
    for (i=0; i<1000; i++) ; // wait for some clock cycles 

    if (HW_LEVELING_ENABLED)
    {
        if (DEBUG_PRINT)
        {
            GEL_TextOut("DEBUG: EMIF1 channel - Launch full levelling\n");
        }

        //clear error status - FIFO_WE_IN_MISALIGNED
        WR_MEM_32(base_addr + 0x00000318,
                  RD_MEM_32(base_addr + 0x00000318) | 0x00000100);
        WR_MEM_32(base_addr + 0x0000031C,
                  RD_MEM_32(base_addr + 0x0000031C) | 0x00000100);
				  
        WR_MEM_32(base_addr + 0x000000D8, 0x80000000);//RDWR_LVL_RMP_CTRL - Enable levelling
        WR_MEM_32(base_addr + 0x000000DC, 0x80000000);//RDWR_LVL_CTRL - Launch full levelling         
 
        //Wait for the levelling procedure to complete
        while((RD_MEM_32(base_addr + 0x000000DC) & 0x80000000) != 0x0);

        //Check for Errors
        if((RD_MEM_32(base_addr + 0x00000004) & 0x70) != 0x0)
        {
            GEL_TextOut("ERROR: HW-Levelling time-out\n");
        }      
    }
    
}

hotmenu AM572x_DDR3_532MHz_Config()
{
    GEL_TextOut("--->>> DDR3 Initialization is in progress ... <<<---\n");

    /* DDR PLL config */
    dpll_ddr_config(532);

    // EMIF - DDR Overall Configuration  -
    if (DEBUG_PRINT)
    {
        GEL_TextOut("DEBUG: Overall DDR configuration\n");
    }

    // EMIF - DDR IOs CONFIG
    if (DEBUG_PRINT)
    {
        GEL_TextOut("DEBUG: EMIF1 and EMIF1 DDR IOs config (CTRL_MODULE_CORE_PAD module)\n");
    }

    WR_MEM_32(0x4A005110, 0x00000000);     // DLL override disable =0 ; enable = 1

    WR_MEM_32(0x4A002E30, 0x80808080);     //CONTROL_DDR3CH1_0 -- channel_1 CMDs / 40Ohm Ron (011) / SR=slowest-3 (111) on CMDs but CLK SR=slow (011) / No pulls (00)
    WR_MEM_32(0x4A002E34, 0x80808080);     //CONTROL_DDR3CH2_0 -- channel_2 CMDs / 40Ohm Ron (011) / SR=slowest-3 (111) on CMDs but CLK SR=slow (011) / No pulls (00)
    WR_MEM_32(0x4A002E38, 0x40404040);     //CONTROL_DDRCH1_0 -- channel_1 DATA byte 0+1 / 40Ohm Ron (011) / SR=faster (001) / Pull-up (10) on DQS / No pull (00) on DQ
    WR_MEM_32(0x4A002E3C, 0x40404040);     //CONTROL_DDRCH1_1 -- channel_1 DATA byte 2+3 / 40Ohm Ron (011) / SR=faster (001) / Pull-up (10) on DQS / No pull (00) on DQ
    WR_MEM_32(0x4A002E40, 0x40404040);     //CONTROL_DDRCH2_0 -- channel_2 DATA byte 0+1 / 40Ohm Ron (011) / SR=faster (001) / Pull-up (10) on DQS / No pull (00) on DQ
    WR_MEM_32(0x4A002E44, 0x40404040);     //CONTROL_DDRCH2_1 -- channel_2 DATA byte 2+3 / 40Ohm Ron (011) / SR=faster (001) / Pull-up (10) on DQS / No pull (00) on DQ
    WR_MEM_32(0x4A002E48, 0x40404040);     //CONTROL_LPDDR2CH1_0 -- channel_1 LPDDR2 CMD PHYs IOs not used on OMAP5432
    //this is RSVD
    WR_MEM_32(0x4A002E4C, 0x80808080);     //CONTROL_CONTROL_LPDDR2CH1_1 -- channel_1 LPDDR2 CMD PHYs IOs not used on OMAP5432

    WR_MEM_32(0x4A002E50, 0xA2084210);     //DDRIO_0 -- VREF cells (CH1 DQ3/0 INT 2uA / Cap to GND / CMD1/0 DDR3 INT-OUT 32uA / Cap to GND)
    WR_MEM_32(0x4A002E54, 0x84210840);     //DDRIO_1 -- VREF cells (CH1 OUT 32uA Cap to GND / CH2 DQ3/0 INT 2uA / Cap to GND / CH2 OUT 32uA Cap to GND)
    WR_MEM_32(0x4A002E58, 0x84210000);     //DDRIO_2 -- VREF cells (LPDDR2 CH1/2 CA INT/OUT - unused on OMAP5432)
    WR_MEM_32(0x4A002E88, 0xA2000000);     //CONTROL_DDRIO_EXT_0


    // EMIF1 and EMIF2 PHYs extra CONFIG - CTRL_MODULE_WKUP
    if (DEBUG_PRINT)
    {
        GEL_TextOut("DEBUG: DDR PHY config (CTRL_MODULE_WKUP module)\n");
    }

    WR_MEM_32(0x4AE0C144, 0x0001C127); //EMIF1_SDRAM_CONFIG_EXT -- cslice_en[2:0]=111 / Local_odt=01 / dyn_pwrdn=1 / dis_reset=0 / rd_lvl_samples=11 (128)
    WR_MEM_32(0x4AE0C148, 0x0000C127); //EMIF2_SDRAM_CONFIG_EXT -- cslice_en[2:0]=111 / Local_odt=01 / dyn_pwrdn=1 / dis_reset=0 / rd_lvl_samples=11 (128)

    if(0)
    {
        WR_MEM_32(0x4AE0CDC8, 0x45145100);     //EFUSE0 -- IOs p/n setting since devices are not yet trimmed
        WR_MEM_32(0x4AE0CDCC, 0x45145100);     //EFUSE1 -- IOs p/n setting since devices are not yet trimmed
        WR_MEM_32(0x4AE0CDD0, 0x45145100);     //EFUSE2 -- IOs p/n setting since devices are not yet trimmed
        WR_MEM_32(0x4AE0CDD4, 0x45145100);     //EFUSE3 -- IOs p/n setting since devices are not yet trimmed
    }

    // EMIF1 controller CONFIG
    if (DEBUG_PRINT)
    {
        GEL_TextOut("DEBUG: EMIF1 ctrl + associated DDR PHYs initial config (EMIF1 module)\n");
    }

    reset_emif_params_ddr3_532();
    set_emif1_params_ddr3_532();
    EMIF_Config(EMIF1_BASE_ADDR);

    
    // EMIF2 controller CONFIG
    if (DEBUG_PRINT)
    {
        GEL_TextOut("DEBUG: EMIF2 ctrl + associated DDR PHYs initial config (EMIF2 module)\n");
    }

    reset_emif_params_ddr3_532();
    set_emif2_params_ddr3_532();
    EMIF_Config(EMIF2_BASE_ADDR);

    if (DEBUG_PRINT)
    {
        GEL_TextOut("DEBUG: Setting LISA maps in non-interleaved dual-EMIF mode \n");
    }    
	
	//MA_LISA_MAP_i      
    WR_MEM_32(0x482AF040, 0xC0600100);
    WR_MEM_32(0x482AF044, 0xC0600100);
    WR_MEM_32(0x482AF048, 0x80600200); 
    WR_MEM_32(0x482AF04C, 0x80600200);    
	
    //DMM_LISA_MAP_i   
    WR_MEM_32(0x4E000040, 0xC0600100);
    WR_MEM_32(0x4E000044, 0xC0600100);
    WR_MEM_32(0x4E000048, 0x80600200);
    WR_MEM_32(0x4E00004C, 0x80600200);   
	
    GEL_TextOut("--->>> DDR3 Initialization is DONE! <<<---\n");
}

Have in mind that this is for AM5728 GP EVM, you may need to adjust some settings according to your use case.

Best Regards,
Yordan

0 Yicheng Bai over 9 years ago in reply to Yordan Kovachev

Intellectual 600 points

Hi Yordan,

Thank you so much for your help. This is great help. Actually I am not sure where to apply these settings with in the DDR_Config.txt as you mentioned. Would you please send me some links that I can go through to apply them or use them to modify certain files?

Best,
Yicheng

0 Yordan Kovachev over 9 years ago in reply to Yicheng Bai

TI__Guru**** 161600 points

Hi Yicheng,

DDR settings are performed once in spl, then u-boot & kernel only use those settings, without additional configuration or tuning of the DDR.

This ddr configuration is done in:
arch/arm/cpu/armv7/omap5/sdram.c

arch/arm/cpu/armv7/omap5/emif.c

Best Regards,
Yordan

0 Yicheng Bai over 9 years ago in reply to Yordan Kovachev

Intellectual 600 points

Hi Yordan,

Thanks for the reply. I found the similar reg values in the file of "board/ti/am57xx/board.c". Which is actually used to tune the DDR settings for this purpose? Or I should modify all of them?

Best, Yicheng

0 Yicheng Bai over 9 years ago in reply to Yordan Kovachev

Intellectual 600 points

Hi Yordan,

I used the CCSv6 + xds220 debugger to test the device and run the scripts to printout ddr leveling output, which are shown as following:

CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 0: 0x00000086
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 1: 0x00000086
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 2: 0x0000008E
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 3: 0x0000008E
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 4: 0x00000000
CortexA15_0: GEL Output:
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO Macro 0: 0x00000041
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO Macro 1: 0x0000003E
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO Macro 2: 0x0000003B
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO Macro 3: 0x0000003C
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO Macro 4: 0x00000000
CortexA15_0: GEL Output:
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 0: 0x00000071
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 1: 0x0000006C
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 2: 0x00000071
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 3: 0x00000071
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 4: 0x00000059
CortexA15_0: GEL Output:
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO Macro 0: 0x00000051
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO Macro 1: 0x0000004C
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO Macro 2: 0x00000051
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO Macro 3: 0x00000051
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO Macro 4: 0x00000059

Are these information useful? How should I use them to tune my DDR parrameters?

Thanks, Yicheng

0 Yordan Kovachev over 9 years ago in reply to Yicheng Bai

TI__Guru**** 161600 points

Hi,

Sorry for the delay.

Yes, modify all of them.

Best Regards,
Yordan

0 Yicheng Bai over 9 years ago in reply to Yordan Kovachev

Intellectual 600 points

Hi Yordan,

Would you please tell me which file to modify? There are several files I found that had the corresponding parameters.

Thanks, yicheng

0 Joshua Vanderpool over 9 years ago in reply to Yicheng Bai

Intellectual 550 points

static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
	.sdram_config_init	= 0x61851b32,
	.sdram_config		= 0x61851b32,
	.sdram_config2		= 0x08000000,
	.ref_ctrl		= 0x000040F1,
	.ref_ctrl_final		= 0x00001035,
	.sdram_tim1		= 0xcccf36ab,
	.sdram_tim2		= 0x308f7fda,
	.sdram_tim3		= 0x409f88a8,
	.read_idle_ctrl		= 0x00050000,
	.zq_config		= 0x5007190b,
	.temp_alert_config	= 0x00000000,
	.emif_ddr_phy_ctlr_1_init = 0x0024400b,
	.emif_ddr_phy_ctlr_1	= 0x0e24400b,
	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
	.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
	.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
	.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
	.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
	.emif_rd_wr_lvl_rmp_win	= 0x00000000,
	.emif_rd_wr_lvl_rmp_ctl	= 0x80000000,
	.emif_rd_wr_lvl_ctl	= 0x00000000,
	.emif_rd_wr_exec_thresh	= 0x00000305
};

/* Ext phy ctrl regs 1-35 */

static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
	0x10040100,
	0x00910091,
	0x00950095,
	0x009B009B,
	0x009E009E,
	0x00980098,
	0x00340034,
	0x00350035,
 	0x00340034,
 	0x00310031,
 	0x00340034,
 	0x007F007F,
 	0x007F007F,
 	0x007F007F,
 	0x007F007F,
 	0x007F007F,
 	0x00480048,
 	0x004A004A,
 	0x00520052,
 	0x00550055,
 	0x00500050,
 	0x00000000,
 	0x00600020,
 	0x40011080,
 	0x08102040,
 	0x0,
 	0x0,
 	0x0,
	0x0,
 	0x0,
 	0x0,
 	0x0,
 	0x0,
 	0x0,
 	0x0
 };

This is from https://git.ti.com/ti-u-boot/ti-u-boot/blobs/master/board/ti/am57xx/board.c

0 Joshua Vanderpool over 9 years ago in reply to Joshua Vanderpool

Intellectual 550 points

Why does ti not use the dra7_ddr3_leveling function in git.ti.com/.../emif-common.c for to get these values?

0 Qing over 9 years ago in reply to Yicheng Bai

Expert 1385 points

Hi，Yicheng：
how to tuning the DDR3 timing on AM5728 ? I have some problem same as you!

Processors

Processors forum

Detail DDR3 software leveling procedure for AM5728 customized board