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AM335x: How to configure a GPIO Interrupt in ISDK?

Other Parts Discussed in Thread: AM3359, SYSBIOS

Hello,

I'm working with the following software configuration:

    • Code Composer Studio version CCS 6.1.1.00022
    • SYS/BIOS 6.42.2.29 Real Time Operating System
    • XDC Tool 3.31.2.38_core
    • Compiler GNU v4.8.4 (Linaro)
    • NDK 2.24.3.35
    • Sysbios sdk 2.1.1.2

 I am trying to configure GPIO0-19pin as a external input interrupt on AM3359 ICE v2.

First, I have configured the pin(GPIO0-19) as input, and I have verified that  I can read the input status Hi and Lo of this pin by polling.

Then, I have tried to generate an interrupt on the rising edge of this input. I've written the following code:

// GPIO config
GPIOSetDirMode(baseAddr, pinNum, GPIO_DIRECTION_INPUT);
GPIODebounceFuncEnable(baseAddr, pinNum, FALSE);

GPIOSetIntrType(baseAddr, pinNum, GPIO_INTR_MASK_RISE_EDGE);

GPIOIntrEnable(baseAddr, 96, pinNum);

GPIOGlobalWakeupDisable(baseAddr);
GPIOWakeupIntrDisable(baseAddr, 96, pinNum);


  // Interrupt config

  gIrqTopZIntrParams.triggerType = INTC_TRIG_RISING_EDGE;
  gIrqTopZIntrParams.priority = 20U;
  gIrqTopZIntrParams.pFnIntrHandler = topZitIsr;
  gIrqTopZIntrParams.pUserParam = 0U;
  gIrqTopZIntrParams.isIntrSecure = FALSE;

   INTCConfigIntr(96,&gIrqTopZIntrParams, FALSE);

I think I've made the right configuration but when I debug my code I never go to my ISR: topZitIsr.

I have already tried to put gIrqTopZIntrParams.pFnIntrHandler = &topZitIsr but I never reach the function.

Is there someone who is able to help me on that case ? Is There any Texas documentation or example that can explain how to configure an interrupt on GPIO on ARM3359 ?

I have found a similar topic in the forum https://e2e.ti.com/support/arm/sitara_arm/f/791/p/498699/1837773#1837773

Thanks a lot for your help.

Laurence

  • Hi,

    I will forward this to the ISDK team.
  • Hi Laurence,
    in SysBios interrupts in general are configured using HWI. Yo can't mix Starterware interrupt control with this.
    The GPIO config stuff is needed too of course.

    For a full GPIO SysBios driver including interrupt support you may have a look at the RTOS SDK. The PDK there does contain the driver and the examples. Over time IA-SDK will be changed to be based on top of PDK anyway. Just didn't happen yet...

    regards,
  • Hello Frank,

    Thanks for your help ( again).
    So I have tried to make what you told me:

    // GPIO config
    GPIOSetDirMode(baseAddr, pinNum, GPIO_DIRECTION_INPUT);
    GPIODebounceFuncEnable(baseAddr, pinNum, FALSE);

    GPIOSetIntrType(baseAddr, pinNum, GPIO_INTR_MASK_RISE_EDGE);

    GPIOIntrEnable(baseAddr, 96, pinNum);

    GPIOGlobalWakeupDisable(baseAddr);
    GPIOWakeupIntrDisable(baseAddr, 96, pinNum);

    // Interrupt config
    Hwi_Params_init(&hwiParams);
    hwiFuncPointer = (Hwi_FuncPtr)TopZIsr;
    hwiParams.priority = 20;
    hwiParams.enableInt = FALSE;
    hwiTopZHndl = Hwi_create(96, hwiFuncPointer, &hwiParams, NULL);
    Hwi_enableInterrupt(96);

    void TopZIsr(void)
    {
    return;
    }

    But, unfortunately, The TopZIsr never happens !
    Can you help me again ?

    Thanks !

    Laurence
  • Laurence,


    at this point I  am lost too. This needs more debug... I am not sure what that does:

    Cazaban Laurence said:
    GPIOGlobalWakeupDisable(baseAddr);
    GPIOWakeupIntrDisable(baseAddr, 96, pinNum);

    From docs I can see that GPIO0 is a bit special as it is also connected to wakeup HW. Never used that.

    So a couple things you can try:

    - check that your signal triggers the interrupt at GPIO level (there are status registers). If not your GPIO module config or the signal itself is bad. If yes, check INTC config..

    - simulate a GPIO IRQ using writes to GPIO_IRQSTATUS_RAW. Again follow the interrupt...

    - try a different GPIO block (not 0). Just a guess...

    - switch to PDK RTOS driver - should be fully tested and supported... This issue is not really IA-SDK related.

    Regards,

     Frank

  • Thanks Frank.

    I'm going to make these tests.

    I will keep you informed.

    See you,


    Laurence

  • Hello Frank,

    I tried to test my GPIO Interrupt...

    I have changed one configuartyion and it works better but it is not totally good...

    In fact, now, I manage to get into my ISR function the first time I have the signal on the GPIO. When I'm int the ISR function, if I read the GPIO_STATUS register, the interrupt is not trigged but if I look at the GPIO_STATUS_RAW register, the GPIO is trigged.

    I think I have forgotten to enable something but what ?

    And after, I don't manage to reach the ISR anymore...

    Can you help me please ?

    Thanks a lot.

    Laurence

  • Laurence,
    actually I don't understand this.
    If you have the interrupt enabled correctly and you get to your ISR the STATUS and STATUS_RAW should both show the IRQ triggered to my mind. Then you need to write to STATUS reg to clear this interrupt bit. As INTC is level sensitive you don't see any new ISR until the source has been cleared by the ISR (and a new event happened). This is assuming SysBios HWI processing is not messing with the GPIO regs...

    Please consider to read chapter 25.3.3 in TRM again. Are you sure there is not other GPIO in that block generating an interrupt? Each block has only two IRQs to host but 32 GPIOs...

    Regards,
  • Sorry, need to correct myself...

    As INTC is level sensitive any not-cleared interrupt will result in an immediate call of the ISR again once it ends... So it looks like your IRQ source gets cleared but the interrupt itself is not enabled anymore.

    Again, this needs live debug I assume...
  • Thanks Frank : it's ok now !
    in fact, I wans cleaning the interrupt...
    Thanks for your help

    Laurence