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AM572x GPEVM shunt regulator protection circuit

prachi panse1
Intellectual 980 points
Other Parts Discussed in Thread: TLVH431

Hi,

In AM572x GPEVM schematics, the shunt regulator circuit used between 3.3V (vddshv) and 1.8V (vdds18v) rails of the processor is to prevent the maximum difference between these rails from exceeding 2V during power down. I have a few queries regarding the same:

1. I understand that this protection circuit will be required in the case when the PMIC supply voltage is discharged within a short time (less than 1 ms). That is because, in that case even though the PMIC will start sequencing down, there will not be input power to supply 1.8V and 3.3V, and both will start to decay.

I wanted to understand the conditions under which this would occur. As per my understanding, if the event triggering the OFF request is VSYS_LO, then the protection circuit is required. It is not required otherwise. Can you please confirm if this is correct?

2. As per our understanding for this circuit to function as regulator, the cathode voltage/current of the shunt regulator - TLVH431 should be fed back to the reference input pin (closed loop mode). However in the EVM this feedback resistor between cathode and reference input is not mounted. Can you please confirm if this resistor is required for the circuit to function correctly? Also, if yes, then what should be the value of this resistor? 

Regards,

Prachi

  • 0
    TI__Guru**** 393215 points
    Hi,

    I will ask the factory team to comment.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 980 points
    Dear Biser,

    Can you please update me on my query?

    Regards,
    Prachi
  • 0 in reply to prachi panse1
    TI__Guru**** 393215 points
    Feedback will be posted directly here when available.
  • 0 in reply to prachi panse1
    TI__Guru 63235 points

    Voltage applied to the REF input is compared to an internal reference voltage and current is shunt from Cathode to Anode as the REF voltage increases above the internal reference voltage. As you mentioned, the REF voltage is normally generated from a voltage divider connected from the Cathode to Anode which allows the TLVH431 to regulate voltage of the Cathode terminal relative to the Anode terminal. This circuit topology is normally used with the Anode terminal connected to ground where the circuit provides a regulated voltage at the Cathode terminal.

    The circuit used on the AM572x GP EVM is trying to maintain a maximum voltage between VDD_SHVx and VDD_1V8. This is why the voltage divider that generates the REF voltage is connected across the two power rails. This allows the circuit to compensating for the base to emitter voltage drop of the PNP transistor. 

    Regards,
    Paul 

  • 0 in reply to peaves
    Intellectual 980 points

    Dear Paul,

    Thanks for your reply. 

    I have a few more questions regarding this protection circuit:

    1. In the AM572x GP EVM Rev A2b, the transistor circuit is present between VDD_1V8 and VDD_SD rails. Why has this been removed in the EVM Rev A3? (The protection circuit for the VDD_SHV5 and VDD_3V3 rails is still retained.)

    2. In the AM572x IDK Rev 1.3b, the protection circuit is present for V3_3D and VSDMMC rails. In this circuit, a 10K resistor is present between the cathode and the reference input, whereas on the AM572x GPEVM, this resistor is not mounted. Also, the resistor between the reference input and the 3.3V supply is mounted in the GP EVM, whereas in the IDK it is not mounted. Can you please explain me why is this difference present?

    Regards,

    Prachi

  • 0 in reply to prachi panse1
    Intellectual 980 points
    Dear Paul,

    Can you please update me on my queries?

    Regards,
    Prachi
  • 0 in reply to prachi panse1
    TI__Guru 63235 points
    The IO cells powered by VDD_SHV5 are different from the other dual-voltage IO cells. We determined the clamp circuit was not needed for VDD_SHV5. That is why it was removed on revision 3A.

    As I mentioned before, the circuit topology used on the GP EVM will compensate for the transistor base/emitter voltage drop. This will decrease the clamp voltage between the two rails by about 0.7 volts relative to the other topology. Both configurations are compliant to the maximum voltage difference requirement.

    The topology used on the GP EVM provides more margin for the maximum voltage difference requirement. However, this smaller voltage difference pulls VDD_1V8 very close to the specified operating voltage for the VDD_1V8 volt rail without power applied to VDD_1V8. So the clamp circuit may be slightly turned on during normal operation. The other topology provides minimum margin for the maximum voltage difference requirement. However, it should be completely turn off during normal operation.

    We purposely implemented different topologies on these boards to build functional history for both options. We have not seen any problems from either topology, so you can use either.

    Regards,
    Paul
  • 0 in reply to peaves
    Intellectual 980 points

    Dear Paul,

    Thank you for the clarification.

    You said that the clamp circuit was not needed for VDD_SHV5 and is removed. However, in the GP EVM revision A3, as compared to revision A2, the circuit on VDD_SD rail is removed and not VDD_SHV5. The protection circuit on VDD_SHV5 and VDD_3V3 rails is still present. Please let me know why this is done.

    Regards,

    Prachi

  • 0 in reply to prachi panse1
    TI__Guru 63235 points
    Opps, my mistake. I was not looking at the schematic when creating my previous reply late last night. I knew we removed the circuit from the power rail sourcing the CD card IO cells. I could not remember the AM572x power rail name, so quickly scrolled up, looked at your question, saw a reference to VDD_SHV5, and used by mistake it in my reply. You are correct the VDD_SD rail which sources VDDSHV8 is the one that we determined does not need the clamp circuit. I'm sorry for the confusion.

    Regards,
    Paul
  • 0 in reply to peaves
    Intellectual 980 points

    Dear Paul,

    Thanks for the clarification.

    Regards,

    Prachi