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How to do DDR calibration for AM335x?

Hello All,


I am learning to write the barebox code for that I am referring PhyBoard-Wega from Phytec.

In there Board folder they have given file named as ram-timings.h, in this file they have mentioned different structures as below:

struct am335x_sdram_timings physom_timings[] = {
    /* 256 MB */
    [PHYFLEX_MT41K128M16JT_256MB] = {
        .regs = {
            .emif_read_latency    = 0x7,
            .emif_tim1        = 0x0AAAD4DB,
            .emif_tim2        = 0x26437FDA,
            .emif_tim3        = 0x501F83FF,
            .sdram_config        = 0x61C052B2,
            .zq_config        = 0x50074BE4,
            .sdram_ref_ctrl        = 0x00000C30,
        },
        .data = {
            .rd_slave_ratio0    = 0x34,
            .wr_dqs_slave_ratio0    = 0x47,
            .fifo_we_slave_ratio0    = 0x9a,
            .wr_slave_ratio0    = 0x7e,
            .use_rank0_delay    = 0x0,
            .dll_lock_diff0        = 0x0,
        },
    },

I am unable to understand from where I will get these values?

I read the datasheet for this part but I didn't found the values.

Que.2 ) Also how to generate the MLO file because when I am building the barebox its simply generating barebox.bin file?