This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM572x USB 3.0 documentation

Other Parts Discussed in Thread: AM5728

Hello team,

Hope you are well.

Also, one of my customers is inquiring about availability of better documentation on USB 3.0 block for AM5728.

We have an NDA in place with the customer. Any chance we have any info that we can share?

Regards,

Randhir

  • Hi,

    I will forward this to the factory team. They will either contact you or respond here.
  • Randhir,

    The engineer who is responsible for documentations is not in office. But does the customer have any specific questions regarding the usb block on am5728? I might be able to answer or find the answer.
  • Randhir, is your customer developing its own USB driver?
  • I am Randhir's customer.

    The primary questions (that I am currently aware of) are:

    1) How many endpoints are supported by the implementation of the USB Controller core? Does it support all EP0-15 IN and OUT, or is more limited? This is documented for the Keystone parts, but not for the AM57xx parts. Some of the competitor parts have very limited number of EPs implemented on the USB3 controller.

    2) Are the FIFOs properly sized (in gadget/device mode) to properly support full super-speed ISOC transmission? We have seen other implementations where the internal core FIFOs are not large enough to fully buffer packets, and as a result there can be DMA errors on transmission (which are obviously not recoverable on ISOCH transfers).

    3) How many isoch periods/packets ahead does the DMA engine in the DWC3 controller work ahead of the current bus period? E.g. -- how late can the data for the  packet payloads hit the buffer and still be picked up by the DMA into the FIFO? This relates to (4) below -- we need to minimize latency for the data transport.

    4) As far as the driver goes, yes -- we have an interest in implementing a device mode driver where the interrupts are handled by an RTOS, and the DMA is coordinated with the DMA buffers of other I/O devices in the part in order to minimize latency for transport of ISOCH data through the part. We have already done such an implementation for DWC2 (I know that DWC3 is very different). So, the documentation that is in the TRM/Data Manual is not sufficient.

    Thanks!

  • Hi,

    B.J. Buchalter said:
    1) How many endpoints are supported by the implementation of the USB Controller core? Does it supportall EP0-15 IN and OUT, or is more limited?

    The USB device controller has 16 bidirectional EPs, including EP0.

    B.J. Buchalter said:
    2) Are the FIFOs properly sized (in gadget/device mode) to properly support full super-speed ISOC transmission?

    I haven't got a test case to verify super-speed Isoch yet, but I don't think there should have any issue. FYI, in high-speed device mode, I am able to transmit 3 1024-byte Isoch packets in a SOF, which is the max defined in the Specs.

    B.J. Buchalter said:
    3) How many isoch periods/packets ahead does the DMA engine in the DWC3 controller work ahead of the current bus period? E.g. -- how late can the data for the  packet payloads hit the buffer and still be picked up by the DMA into the FIFO? This relates to (4) below -- we need to minimize latency for the data transport.

    The DMA is wrapped inside the USB IP, and transparent to sw. I don't have such latency data.

    Re #4, please note that we don't provide technical support for customers implementing non-Linux driver for this USB controller. Linux kernel is reference we provide.

  • Hi Bin,

    Thanks for the feedback.

    Re #1 -- you folks should put that info in the webpage, the datasheet and the TRM; it is a significant feature that competitive parts don't have.

    So, re: (3) - I think it must be documented somewhere. When you have a chain of TD's how many can be processed before the USB host sends the token to have the device transmit the packet? For example, if it is one packet, then if you submit a chain of TDs, the DMA would start to read the first packet into the FIFO before the USB starts to transmit. If this is the case, you could queue up packets for buffers that still have to be written. OTOH, if the DMA works 3 packets ahead, you would either need to queue the TD "just in time" or understand that the DMA for placing data in the buffer needs to have a guard-band for 3 packets' worth of data.

    This question applies especially in the case of using the Linux gadget driver framework, as it is unlikely to be able to queue the packets "just in time" - so if I am forced to use the Linux driver, I do need to understand how far ahead of the current isoch period the DMA will be working to ensure the that the gap between the DMA filling the buffer and the DMA reading out the buffer is big enough...

    re: (4) I am not looking for technical support - just documentation.
  • Team,
    Any feedback on B.J's response below?
    We have an NDA in place with the customer and is there any documentation that we can share that would help?

    Regard,
    Randhir
  • Randhir,
    Sorry, we missed this one...our apps team will reply soon.
  • B.J.,
    The level of detail you are requesting is outside the bounds of our support model for this device.

    We do provide driver examples in our RTOS/Starterware offerings (in addition to having a mainline Linux driver) for this product that may help you achieve your goal.
  • Hi -DK- san,

    AM57x has the Synopsys DWC3 USB controller as described here: http://processors.wiki.ti.com/index.php/Linux_Core_DWC3_User%27s_Guide

    Does access to the information which is not documented in TRM for the USB controller require a special NDA with Synopsys?

    Best regards,

    Daisuke

  • Maeda-san,

    It would require a special 3-way NDA with TI+Synopsys.

    Please note that the TRM+SDK provides sufficient documentation for all supported activities. TI does not support customer driver development for this IP.

  • -DK- san,

    Thank you for your reply.

    If our customer demands the special NDA for the further information, should I contact my local TI representative?

    Best regards,

    Daisuke

  • What need would this documentation address? If they have specific questions, they should post them in the forum.
  • -DK- san,

    Thank you for your reply.

    I hear the specific questions that they have.

    Best regards,

    Daisuke