Hello team,
Hope you are well.
Also, one of my customers is inquiring about availability of better documentation on USB 3.0 block for AM5728.
We have an NDA in place with the customer. Any chance we have any info that we can share?
Regards,
Randhir
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Hello team,
Hope you are well.
Also, one of my customers is inquiring about availability of better documentation on USB 3.0 block for AM5728.
We have an NDA in place with the customer. Any chance we have any info that we can share?
Regards,
Randhir
I am Randhir's customer.
The primary questions (that I am currently aware of) are:
1) How many endpoints are supported by the implementation of the USB Controller core? Does it support all EP0-15 IN and OUT, or is more limited? This is documented for the Keystone parts, but not for the AM57xx parts. Some of the competitor parts have very limited number of EPs implemented on the USB3 controller.
2) Are the FIFOs properly sized (in gadget/device mode) to properly support full super-speed ISOC transmission? We have seen other implementations where the internal core FIFOs are not large enough to fully buffer packets, and as a result there can be DMA errors on transmission (which are obviously not recoverable on ISOCH transfers).
3) How many isoch periods/packets ahead does the DMA engine in the DWC3 controller work ahead of the current bus period? E.g. -- how late can the data for the packet payloads hit the buffer and still be picked up by the DMA into the FIFO? This relates to (4) below -- we need to minimize latency for the data transport.
4) As far as the driver goes, yes -- we have an interest in implementing a device mode driver where the interrupts are handled by an RTOS, and the DMA is coordinated with the DMA buffers of other I/O devices in the part in order to minimize latency for transport of ISOCH data through the part. We have already done such an implementation for DWC2 (I know that DWC3 is very different). So, the documentation that is in the TRM/Data Manual is not sufficient.
Thanks!
Hi,
B.J. Buchalter said:1) How many endpoints are supported by the implementation of the USB Controller core? Does it supportall EP0-15 IN and OUT, or is more limited?
The USB device controller has 16 bidirectional EPs, including EP0.
B.J. Buchalter said:2) Are the FIFOs properly sized (in gadget/device mode) to properly support full super-speed ISOC transmission?
I haven't got a test case to verify super-speed Isoch yet, but I don't think there should have any issue. FYI, in high-speed device mode, I am able to transmit 3 1024-byte Isoch packets in a SOF, which is the max defined in the Specs.
B.J. Buchalter said:3) How many isoch periods/packets ahead does the DMA engine in the DWC3 controller work ahead of the current bus period? E.g. -- how late can the data for the packet payloads hit the buffer and still be picked up by the DMA into the FIFO? This relates to (4) below -- we need to minimize latency for the data transport.
The DMA is wrapped inside the USB IP, and transparent to sw. I don't have such latency data.
Re #4, please note that we don't provide technical support for customers implementing non-Linux driver for this USB controller. Linux kernel is reference we provide.
Hi -DK- san,
AM57x has the Synopsys DWC3 USB controller as described here: http://processors.wiki.ti.com/index.php/Linux_Core_DWC3_User%27s_Guide
Does access to the information which is not documented in TRM for the USB controller require a special NDA with Synopsys?
Best regards,
Daisuke
Maeda-san,
It would require a special 3-way NDA with TI+Synopsys.
Please note that the TRM+SDK provides sufficient documentation for all supported activities. TI does not support customer driver development for this IP.