Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.

  • State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 2 answers
  • Subscribers 100 subscribers
  • Views 2836 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM571x support for dual die DDR3

Tony Tang
Mastermind 27011 points
Other Parts Discussed in Thread: AM5718

My customer use 2 pcs x16bit 8Bit DDR3 memory Dual-Die DDR3 on AM5718, got abnormal result, access 0x80000000-0xBFFFFFFF is right, access 0xC0000000-0xD0000000 also right, but access across 0xB0000000-0xD0000000 result system hang, seems the range across dual die, I searched e2e got AM437x doesn't support dual die, but not sure AM571x.

In datasheet sprs919k page 5 revision history: Dual-Rank memory support is removed.

Are Dual-die and Dual-Rank same thing?

Is dual-die is support, please let us know what need to be set to enable dual-die support.

  • 0
    TI__Mastermind 27011 points

    I found on latest AM5718 TRM page 3283.

    memory manager (DMM) module

    • Supports SDRAM devices with one, two, four or eight internal banks

    • Supports SDRAM devices with single or dual die packages

    on page 3284: 

    The EMIF module does not support:

    • Burst chop for DDR3

    • Interleave burst type

    • Auto precharge because of better Bank Interleaving performance

    • DLL disabling from EMIF side

    • SDRAM devices with more than one die, or topologies which require more than one chip select on a

    single EMIF channel

    So it supported on not support dual die DDR3 device?

    I past the schematic below and attached the DDR datasheet, please advise...

     


    1410026905-01 copy.pdf

  • 0 in reply to Tony Tang
    TI__Guru**** 393215 points
    The DDR experts have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Genius 9625 points

    As noted in the TRM, the device does not support twin-die configurations - the twin-die device has 2 loads on the data bus which is not supported on AM571x.

    Regards, Siva

  • 0 in reply to sivak
    TI__Mastermind 27011 points

    Siva.

    Thanks for confirmation, I have some more questions need your help.

    #1. Why on page 3283 said support dual die. on page 3284 said not support, which is correct? or we are misunderstanding the description?

    #2. if not support, what is the estimated result with dual die device? Will 2 load lead to bad SI then result in data error? or can't address such memory at all?

    #3. Now we can access either die correctly, but fail when address walk over one die to next die, is it explainable?

  • 0 in reply to Tony Tang
    TI__Genius 9625 points

    Tony Tang said:

    #1. Why on page 3283 said support dual die. on page 3284 said not support, which is correct? or we are misunderstanding the description?

    Page 3283 describes the generic features of the memory controller and the Page 3284 describes the features that are unsupported from the list of the generic features. That is the reason why the list of features not listed is specifically called out for in the TRM. Does this clarify your confusion?

    Tony Tang said:

    #2. if not support, what is the estimated result with dual die device? Will 2 load lead to bad SI then result in data error? or can't address such memory at all?

    I cannot provide definitive guidance on this since we have no validation with such a configuration. However, the result of excessive loads on the data bus could either lead to signal integrity and/or timing violations. If the configuration is set correctly, the memory can be addressed, but the memory READ/WRITE access might not be reliable

    Tony Tang said:

    #3. Now we can access either die correctly, but fail when address walk over one die to next die, is it explainable?

    This fail signature might be related to some other configuration issue. Since this is not a valid configuration that is supported on this device, I suggest you replace the memory part with a single die device

    Regards, Siva