AM3351: CPU frequency

Thanks for the reply, we are using that configuration and I have reviewed those links previously. As can be seen in the original post, cpufreq is enabled in the kernel config but for some reason the paths don't exist.

Tim,

Check your linux-4.4.12/.config file, make sure it has the below options:

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_STAT_DETAILS=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
CONFIG_ARM_TI_CPUFREQ=y
# CONFIG_QORIQ_CPUFREQ is not set

Also in your DTS file, make sure you have the opp table as defined in the AM335x TI EVM DTS file am33xx.dtsi

cpus {
        #address-cells = <1>;
        #size-cells = <0>;
        cpu@0 {
            compatible = "arm,cortex-a8";
            enable-method = "ti,am3352";
            device_type = "cpu";
            reg = <0>;

            operating-points-v2 = <&cpu0_opp_table>;
            ti,syscon-efuse = <&scm_conf 0x7fc 0x1fff 0>;
            ti,syscon-rev = <&scm_conf 0x600>;

            clocks = <&dpll_mpu_ck>;
            clock-names = "cpu";

            clock-latency = <300000>; /* From omap-cpufreq driver */
            cpu-idle-states = <&mpu_gate>;
        };

        idle-states {
            mpu_gate: mpu_gate {
                compatible = "arm,idle-state";
                entry-latency-us = <40>;
                exit-latency-us = <90>;
                min-residency-us = <300>;
                ti,idle-wkup-m3;
            };
        };
    };

cpu0_opp_table: opp_table0 {
        compatible = "operating-points-v2";

        /*
         * The three following nodes are marked with opp-suspend
         * because the can not be enabled simultaneously on a
         * single SoC.
         */
        opp50@300000000 {
            opp-hz = /bits/ 64 <300000000>;
            opp-microvolt = <950000 931000 969000>;
            opp-supported-hw = <0x06 0x0010>;
            opp-suspend;
        };

        opp100@275000000 {
            opp-hz = /bits/ 64 <275000000>;
            opp-microvolt = <1100000 1078000 1122000>;
            opp-supported-hw = <0x01 0x00FF>;
            opp-suspend;
        };

        opp100@300000000 {
            opp-hz = /bits/ 64 <300000000>;
            opp-microvolt = <1100000 1078000 1122000>;
            opp-supported-hw = <0x06 0x0020>;
            opp-suspend;
        };

        opp100@500000000 {
            opp-hz = /bits/ 64 <500000000>;
            opp-microvolt = <1100000 1078000 1122000>;
            opp-supported-hw = <0x01 0xFFFF>;
        };

        opp100@600000000 {
            opp-hz = /bits/ 64 <600000000>;
            opp-microvolt = <1100000 1078000 1122000>;
            opp-supported-hw = <0x06 0x0040>;
        };

        opp120@600000000 {
            opp-hz = /bits/ 64 <600000000>;
            opp-microvolt = <1200000 1176000 1224000>;
            opp-supported-hw = <0x01 0xFFFF>;
        };

        opp120@720000000 {
            opp-hz = /bits/ 64 <720000000>;
            opp-microvolt = <1200000 1176000 1224000>;
            opp-supported-hw = <0x06 0x0080>;
        };

        oppturbo@720000000 {
            opp-hz = /bits/ 64 <720000000>;
            opp-microvolt = <1260000 1234800 1285200>;
            opp-supported-hw = <0x01 0xFFFF>;
        };

        oppturbo@800000000 {
            opp-hz = /bits/ 64 <800000000>;
            opp-microvolt = <1260000 1234800 1285200>;
            opp-supported-hw = <0x06 0x0100>;
        };

        oppnitro@1000000000 {
            opp-hz = /bits/ 64 <1000000000>;
            opp-microvolt = <1325000 1298500 1351500>;
            opp-supported-hw = <0x04 0x0200>;
        };
    };

    pmu {
        compatible = "arm,cortex-a8-pmu";
        interrupts = <3>;
    };

Regards,
Pavel

Hi there,

Thanks for the reply. Here's the relevant section of our dtsi file:

Which seems to be identical to what you suggested. It is also included in our dts file: "#include "am33xx.dtsi""

And here's the relevant section of our config file:

which also seems to be what you suggested.

Any other ideas/suggestions? Thanks in advance for your time.

Hi Pavel,

Thanks for the reply. I've reviewed the threads. In the second thread, it is noted that the following option should be present:

CONFIG_GENERIC_CPUFREQ_CPU0=y

But it was not present in your previous reply. Can you confirm that the kernel config options I posted a couple posts ago are all that is necessary?

In the third thread, I found this:

"cpufreq" relies upon the regulator framework in order to change voltage.  In turn, the regulator framework uses I2C0 to communicate to the PMIC.  On your board, do you have I2C0 connected to the PMIC?  Is I2C0 enabled in your kernel configuration, and also pin mux'ed correctly?

I'm not sure that we have a PMIC. I'll check with the hardware engineer about this.

I've attached the requested boot log.

EDIT: We are using the AM3351BZCE60, which should be capable of 600Mhz?

bootlog.rtf

Tim Elmore said:

Thanks for the reply. I've reviewed the threads. In the second thread, it is noted that the following option should be present:

CONFIG_GENERIC_CPUFREQ_CPU0=y

But it was not present in your previous reply. Can you confirm that the kernel config options I posted a couple posts ago are all that is necessary?

This option is valid for older kernel (3.x) and SDK. There is no such option for kernel 4.4.12. Your kernel config options looks to be correct.

Tim Elmore said:

"cpufreq" relies upon the regulator framework in order to change voltage.  In turn, the regulator framework uses I2C0 to communicate to the PMIC.  On your board, do you have I2C0 connected to the PMIC?  Is I2C0 enabled in your kernel configuration, and also pin mux'ed correctly?

I'm not sure that we have a PMIC. I'll check with the hardware engineer about this.

Yes, the issue might be in the PMIC (or the lack of it). On AM335x EVM which comes with TPS65910 we have the below boot log with the pre-built zImage from PSDK 3.00.00.04

[    1.959123] tps65910 0-002d: No interrupt support, no core IRQ
[    1.988005] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
[    1.995859] omap_i2c 4802a000.i2c: bus 1 rev0.11 at 100 kHz
[    2.002424] omap_hsmmc 48060000.mmc: Got CD GPIO
[    2.007508] vmmc: supplied by vbat
[    2.049688] vdd_mpu: supplied by vbat

And after boot up we have:

am335x-evm login: root
root@am335x-evm:~# cd /sys/devices/system/cpu/cpu0/cpufreq
root@am335x-evm:/sys/devices/system/cpu/cpu0/cpufreq# ls
affected_cpus                  cpuinfo_min_freq               scaling_available_frequencies  scaling_driver                 scaling_min_freq
cpuinfo_cur_freq               cpuinfo_transition_latency     scaling_available_governors    scaling_governor               scaling_setspeed
cpuinfo_max_freq               related_cpus                   scaling_cur_freq               scaling_max_freq               stats
root@am335x-evm:/sys/devices/system/cpu/cpu0/cpufreq#

Tim Elmore said:

We are using the AM3351BZCE60, which should be capable of 600Mhz?

Yes, this device support 600-MHz Cortex-A8

Make sure also sysfs is mounted on your board.


Regards,
Pave

Thanks for the reply. So it seems CPUFreq isn't an option on our current board.

Where else does CPU frequency get set? I saw in u-boot where the e-fuses get checked:

Tim Elmore said:

So I pulled the CM_CLKSEL_DPLL_MPU register (0x44E0042c)

and it yielded:

0x00012C17

Which is a multiplier of 300 and a divisor of 24, and the input clock is 24, so that’s a clock speed of 300Mhz.

Tim,

Can you provide also the below registers values:

DEVICE_ID/0x44E10600

CONTROL_STATUS/0x44E10040

CM_IDLEST_DPLL_MPU/0x44E00420

CM_CLKMODE_DPLL_MPU/0x44E00488

CM_DIV_M2_DPLL_MPU/0x44E004A8

You can take these values from the u-boot prompt with md command, example:

Press SPACE to abort autoboot in 2 seconds
=> md 0x44E10600 1
44e10600: 0b94402e                               .@..

On the AM335x EVM rev 1.4a I have the below values:

DEVICE_ID[31:28] DEVREV = 0 - silicon revision 1.0
CONTROL_STATUS[23:22] sysboot1 = 0x1  - 24MHz CLK_M_OSC
CM_CLKSEL_DPLL_MPU = 0x0002D017
CM_IDLEST_DPLL_MPU = 0x00000001
CM_CLKMODE_DPLL_MPU = 0x00000007
CM_DIV_M2_DPLL_MPU = 0x00000201 (M2 = 1)

Thus I have 720MHz for Cortex-A8.

am335x_get_efuse_mpu_max_freq() return MPUPLL_M_720, as I have PG 1.0 (silicon revision 1.0) device on the AM335x EVM rev 1.4a : XAM3359ZCZ

Regards,
Pavel

Tim Elmore said:

Where else does CPU frequency get set? I saw in u-boot where the e-fuses get checked:

case AM335X_ZCE_600:

return MPUPLL_M_600;

Shouldn't that be setting the CPU to 600Mhz? I've also checked the e-fuse registers, which confirmed 600Mhz capability. If you could let me know where the 300Mhz setting might be coming from I would be much obliged.

So am335x_get_efuse_mpu_max_freq() return MPUPLL_M_600 which is correct in your case - AM3351BZCE60 device. Then I think the lack of PMIC is preventing the u-boot to set this 600MHz.

What is your board file? On AM335x EVM, the board file is:

u-boot-2016.05/board/ti/am335x/board.c

/* Get the frequency */
    dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); //you have MPUPLL_M_600 here

.......

else {
        int sil_rev;

        /*
         * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
         * MPU frequencies we support we use a CORE voltage of
         * 1.1375V.  For MPU voltage we need to switch based on
         * the frequency we are running at.
         */
        if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
            return;

/*
         * Depending on MPU clock and PG we will need a different
         * VDD to drive at that speed.
         */
        sil_rev = readl(&cdev->deviceid) >> 28;
        mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
                              dpll_mpu_opp100.m);

        /* Tell the TPS65910 to use i2c */
        tps65910_set_i2c_control();

        /* First update MPU voltage. */
        if (tps65910_voltage_update(MPU, mpu_vdd))
            return;

        /* Second, update the CORE voltage. */
        if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
            return;

        /* Set CORE Frequencies to OPP100 */
        do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
    }

    /* Set MPU Frequency to what we detected now that voltages are set */
    do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);

As you can see the code that set up these 600MHz is dependent on the PMIC. Note also that to setup 600MHz (OPP100), VDD_MPU and VDD_CORE should be at 1.1V, while for 300MHz (OPP50) they should be 0.95V. You can check what voltage you have there also.

Regards,
Pavel

Hi Brad, thanks for the reply. I've attached the output from those commands, it seems to indicate 300Mhz as well.

Clock Diags.rtf

Thanks for the reply - this is helpful!

We are using u-boot-2016.05/board/ti/am335x/board.c.

I have confirmed that we are supplying 1.1v to VDD_CORE. What is the recommended way to modify board.c to set 600Mhz without a PMIC?

Alternatively if there is a way to change the clock speed once booted, that is acceptable too. Only need 600Mhz once booted.

Hi Pavel,

Thanks for all the help - this is resolved. The clocks were not getting set due to the return after the i2c check for PMIC. So I modified the code to set the clocks before returning, since in our case we always run at 600Mhz and have the correct voltage supplied.

Thanks again for the assistance.