Linux/PROCESSOR-SDK-AM335X: NAND not detected on custom board

Phil Chang

Intellectual 580 points

Part Number: PROCESSOR-SDK-AM335X
Other Parts Discussed in Thread: AM3352

Tool/software: Linux

Hello,

My custom board with am3352 main chip, and the nand flash is "micron mt29f1g08abaeawp".

I follow the document from u-boot step to enable the nand flash, but still cannot detect it in uboot,

which means the command "nand info" and "nand device" has nothing...

I found some weird on the custom board schematic, the NAND flash SMI_WP pin connect to GPMC_CLK,

is that correct?

here is the part of schematic:

And the NAND flash schematic:

from the TRM, the GPMC_WP pin connect to NAND flash WP pin, but we connect to RMII phy, is it cause that the board cannot detect the nand flash?

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Hi,

This connection definitely is not correct. However you can eliminate it for the moment by removing the jumper. I don't think this is the reason the NAND doesn't work. What Linux version are you using?

0 Phil Chang over 9 years ago in reply to Biser Gatchev-XID

Intellectual 580 points

Thanks for reply,
for now, I just live in u-boot, try to boot via sd-card and write MLO to nand, so I need to do_nand_init fine,
So if I disconnect the SMI_WP pin, the nand "should" be detected?

0 Biser Gatchev-XID over 9 years ago in reply to Phil Chang

TI__Guru**** 393215 points

What is the U-boot version? Where did you take it from?

0 Phil Chang over 9 years ago in reply to Biser Gatchev-XID

Intellectual 580 points

The SDK form Ti website version 2.00, and the u-boot-2015.07.xxxxx

In my trace path, the entrance is drivers/mtd/nand/nand.c

static void nand_init_chip(int i)
{
    struct mtd_info *mtd = &nand_info[i];
    struct nand_chip *nand = &nand_chip[i];
    ulong base_addr = base_address[i];
    int maxchips = CONFIG_SYS_NAND_MAX_CHIPS;

    if (maxchips < 1)
        maxchips = 1;

    mtd->priv = nand;
    nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;

    if (board_nand_init(nand)){
        printf("board_nand_init failed! return...");
        return;
    }

    if (nand_scan(mtd, maxchips)){   //Failed here
        printf("nand_scan failed! return...");
        return;
    }

    printf("goto nand_register..\n");
    nand_register(i);
}

The nand_scan is failed.. so cannot goto nand_register

here is my pin mux:

board/ti/am335x/mux.c

#ifdef CONFIG_NAND
static struct module_pin_mux nand_pin_mux[] = {
    {OFFSET(gpmc_ad0),  (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0  */
    {OFFSET(gpmc_ad1),  (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1  */
    {OFFSET(gpmc_ad2),  (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2  */
    {OFFSET(gpmc_ad3),  (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3  */
    {OFFSET(gpmc_ad4),  (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4  */
    {OFFSET(gpmc_ad5),  (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5  */
    {OFFSET(gpmc_ad6),  (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6  */
    {OFFSET(gpmc_ad7),  (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7  */
#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
    {OFFSET(gpmc_ad8),  (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8  */
    {OFFSET(gpmc_ad9),  (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9  */
    {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
    {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
    {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
    {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
    {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
    {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
#endif
    {OFFSET(gpmc_wait0),    (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
//  {OFFSET(gpmc_wpn),  (MODE(7) | PULLUP_EN)},        /* nWP */
    {OFFSET(gpmc_clk),  (MODE(7) | PULLUP_EN)}, // the wired pin
    {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)},        /* nCS */
    {OFFSET(gpmc_wen),  (MODE(0) | PULLDOWN_EN)},      /* WEN */
    {OFFSET(gpmc_oen_ren),  (MODE(0) | PULLDOWN_EN)},      /* OE */
    {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)},      /* ADV_ALE */
    {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)},      /* BE_CLE */
    {-1},
};

the wired pin is WP, according my schematic, I should choose gpmc_clk, right?

BTW my NAND flash is micron mt29f1g08abaeawp(SLC) , x8 width

0 Biser Gatchev-XID over 9 years ago in reply to Phil Chang

TI__Guru**** 393215 points

I have forwarded this to the software team. They will respond here.

0 Phil Chang over 9 years ago in reply to Biser Gatchev-XID

Intellectual 580 points

Many many many thanks!

0 Yordan Kovachev over 9 years ago in reply to Phil Chang

TI__Guru**** 161600 points

Hi Phil,

1. If you removed the jumper as Biser suggested, you should've disabled the write protect of your nand chip and should be able to detect the nand flash. However in this case you need to verify that your GPMC is configured to work in asynchronous mode. You should verify that
GPMC_CONFIG1_x[27]WRITETYPE = 0h => Write Asynchronous
GPMC_CONFIG1_x[29]READTYPE = 0h => Read Asynchronous
x = 0..6, depending on which cs you use.
And if this is not the case try setting the above bit fields to 0x0.

2. If you didn't remove the jumper, then the following line:
{OFFSET(gpmc_clk), (MODE(7) | PULLUP_EN)}, // the wired pin ==> sets the pin as GPIO and configures its level to 0x1 (pullup).
will enable the write protect and you will lock your nand. So you should try to output 0x0 on the gpio.

Best Regards,
Yordan

0 Phil Chang over 9 years ago in reply to Yordan Kovachev

Intellectual 580 points

Many thanks Yordan & Biser
After check, follow:
GPMC_CONFIG1_x[27]WRITETYPE = 0h => Write Asynchronous
GPMC_CONFIG1_x[29]READTYPE = 0h => Read Asynchronous
It's work, Thanks again!

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Linux/PROCESSOR-SDK-AM335X: NAND not detected on custom board