TMS320C6678: MAR configuration for Cache/Prefetch with OpenMP Runtime

Hi Naoki,

I've forwarded this to the OpenMP experts. Their feedback should be posted here.

BR
Tsvetolin Shulev

Hello,

Thank you for responding, but do you have any update on this ?

Best Regards,
Naoki

Ajay,

Sorry for my delayed response. Ok, so what does bit2 of MAR mean ?
CorePac user guide does not mention about bit2/3 on MAR register. They are regarded as reserved. Can you clarify about this ?

Also, SYS/BIOS Cache module generates MAR values for its startup configuration. If we don`t intentionally override them in *.cfg file, the following MAR values are set to MAR registers before reaching app main() function.

Please find your C:\ti\bios_6_46_04_53\packages\ti\sysbios\family\c66\Cache.xs

    for (var i=0; i < Cache.marvalues.length; i++) {
        if (i == 0) {
            /* enable the 'PC' bit */
            Cache.marvalues[i] = 0x1;
        }
        else if (i > 0 && i <= 11) {
            /* all bits are disabled */
            Cache.marvalues[i] = 0x0;
        }
        else if (i > 11 && i <= 15) {
            /* enable 'PC', 'PCX', and 'PFX' */
            Cache.marvalues[i] = 0xD;
        }
        else {
            /* enable 'PCX' and 'PFX' */
            Cache.marvalues[i] = 0xC;
        }
    }

The above values (Cache_marvalues) are set to MARs in Cache_startup(). Please take a look at  C:\ti\bios_6_46_04_53\packages\ti\sysbios\family\c66\Cache.c also.

/*
 *  ======== Cache_startup ========
 *  Sets the default cache size and MAR register values.
 */
Void Cache_startup()
{
    UInt32 i;
    Cache_Size cacheSize;

    Cache_getL1DInitSize(&cacheSize);
    Cache_getL1PInitSize(&cacheSize);
    Cache_getL2InitSize(&cacheSize);
    Cache_setSize(&cacheSize);

    /*
     *  MAR0-15 is ready-only and will generate an exception
     *  when Memory protection is enabled. Start at MAR16.
     */
    for (i = 16; i < 256; i++) {
        Cache_setMar((Ptr)(i << 24), 1, Cache_marvalues[i]);
    }
}

In summary, BIOS sets MAR values only for DDR3 region (MAR16~ for DDR3) by default and it intentionally sets PCX (bit2) and PFX(bit3) bits on MAR registers.

If users want to enable caching/prefetching for DDR3, they can overwrite 0x9 to MARs in their application, but at this point, they can force PCX bit to 0 because user guide does not mention about this bit in detail. In this scenario, does the caching/prefetching still work correctly for DDR3 ?

Best Regards,
Naoki

Sorry for rushing you, but i`m really waiting for your response.
Thank you in advance.

MAR register Bits:
Bit 0: PC
Bit 1: WTE
Bit 2: PCX
Bit 3: PFX

The PCX bit indicates whether a given address range is cacheable in an external cache
such as MSMC
The PFX bit indicates whether a given address range is prefetchable by external prefetching engines.

Ajay Jayaraj said:

The PCX bit indicates whether a given address range is cacheable in an external cache
such as MSMC

C667x does not support cache on MSMC. So I think it is okay for users to set this bit to 0 (disabled). Correct, right ?
Once this is clarified, I`ll close the thread.

Best Regards,
Naoki

Hi,

MSMC is always cachable. See the C66x corepac 4.4.5: To support MSMC, the L2 memory controller forces the MAR.PC bit corresponding to
the MSMC memory to 1 (always MAR12.PC through MAR15.PC). This makes the
MSMC memory always cacheable within L1D when accessed by its primary address
range. Secondary ranges may exist due to aliases configured with XMC’s MPAX
unit—these ranges are governed by their corresponding MAR.PC bits.

If you want to make MSMC uncachable, you need to use MPAX to map it to another location then set the MAR register.

Regards, Eric

Eric,

I know that.

What I really don`t understand is the usage of PCX bit. Ajay said, "The PCX bit indicates whether a given address range is cacheable in an external cache such as MSMC". Because MSMC does not support to configure cache in MSMC, I mean, MSMC does not look like L2SRAM/Cache and works as SRAM only. I guessed PCX bit was reserved for future enhancement, i.e., external Cache in MSMC.
That`s why I wondered if PCX bit could be regarded as "dont`t care" and the value of 0 or 1 would be acceptable for the current C66x users (There is no difference between PCX=0 and PCX=1 in cache behavior on current keyStone I family). I`m waiting for your answer about it.

Best Regards,
Naoki

Ok. Thanks for the clarification. I close the thread.

Best Regards,
Naoki

But when MAR is set to 0x3, the caches since change , they are not working 4-way. Like a one way cache. When a process accesses two blocks of DDR,for example 0x81000000 and 0x82000000, setting MAR to 3 is slower than 1.
Why is it?