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am3358: LCD Hsync and Vsync phasing

Dan Beadle
Intellectual 800 points
Part Number: AM3358

After successfully interfacing several LCD displays, I am having trouble with one particular interface.   The display requires that HSync and VSync fall simultaneously.  

I is there any way to configure the chip to do this?  I have tried various combinations of Timing2 register.  The logic analyzer confirms all other signals are correct.

  • 0
    Intellectual 800 points
    What I see is that the rising edge of HSync clocks VSync low. This violates the display requirement for both to go active simultaneously.
  • 0 in reply to Dan Beadle
    TI__Guru**** 393215 points
    Have you checked if this can be achieved by manipulating RASTER_TIMING_2 register values? Section 13.5.1.13 of the AM335x TRM Rev. P.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 800 points

    Thanks. I had been working with Rev O. Rev P adds a timing diagram in 13-27. 

    Notice that is shows VSync changing on the leading edge of HSync.

    I tried all combinations of RasterTiming2 PHSVS_RF and PHSVS_ON_OFF and the trailing edge of HSYNC leads VSync.   I tried this with IVS/IHS both clear and set with same results other than inversion.

    The big picture looks right.  I have verified the number of clocks for Hsw, Hbp, Hfp, Vsw, Vbp and Vfp as well as the data clocks.   The capture below shows syncs leading up to Vsync:

    But looking at the detail, it is clear that I have Hsync leading Vsync

    This doesn't match the description in 13-27.  If I can produce 13-27 where Vsync and Hsync activate at the same time, I meet the LCD requirements.  

    I don't see any other registers that would affect the sync phasing;

    Any suggestions?  Or is the figure in the TRM wrong?

  • 0 in reply to Dan Beadle
    Intellectual 800 points

    The timing diagram in TRM Rev P appears to be incorrect. 

    That said, it was not the issue; instead, it was an error I made in the DMA transfer length switching from WVGA to VGA, unrelated to the issue.   I increased the Vsyncwidth to > 1 and the LCD module was happy. as it found both Vsync and Hsync low at the same time. 

    Thanks for your help.