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AM3352: McASP master clock configuration

Paul Richards
Prodigy 205 points
Part Number: AM3352
Other Parts Discussed in Thread: TLV320AIC3106

Hi,

I previously raised a ticket in the data converters forum for details on interfacing a AM335x with some TLV320AIC3106 codecs in a TDM topology (https://e2e.ti.com/support/data_converters/audio_converters/f/64/p/664803/2443731). I'd like to confirm if the AM335x can master the required bit and frame clocks, without usage of the external high speed master clock (AHCLKX).  We require up to 6 timeslots in each direction at 8 kHz / 16-bits.

Although the TLV320AIC3106 only seems to care for the frame timing, bit offset and slot width, reading the AM335x it appears that a) the XCLK will need to be an integral division of the internal 24 MHz AUXCLK, and b) the frame timing is configurable only in multiples of timeslots and not bit clocks. I.e. not possible to generate the bit clock at a multiple of 768 kbps, and not possible to support partial timeslots?

I.e. I'd like to confirm that there isn't anything obvious I'm missing before we update the design to either supply an appropriate AHCLKX (e.g. as per the BBB design), or have one of the codecs master the timing.

Regards,

Paul

  • 0
    TI__Guru**** 393215 points
    The factory team have been notified. They will respond here.
  • 0
    TI__Mastermind 30140 points
    Hi Paul,

    I think you nailed it.

    XCLK is only integer divisible from AUXCLK.
    So with 24MHz AUXCLK, you cannot evenly divide to get 768k (or any other BCLK that allows 6+ TDM slots at 8kHz/16-bits)

    You can change the input clock that supplies AUXCLK, externally drive ACLKX (BCLK) with 768kHz, or a clock into AHCLK that can be integer divided to get 768k.

    McASP does not support partial time slots. McBSP has some interesting dual-phase framing where the word lengths can be variable lengths in each phase. But there is no McBSP on AM335x.

    Hope this helps (and sorry for the delay),
    Mark
  • 0 in reply to Mark M
    Prodigy 205 points

    Hi Mark,

    Thanks very much for the response.

    Understood, in which case I think we'll look to add an external clock with appropriate ratio that can drive both AHCLK and and the TLV320AIC3106 master clocks (for use without PLL).

    Regards,

    Paul