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RTOS/AM5726: SMP support

Mukul Bhatnagar
Guru* 84435 points
Part Number: AM5726
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

Posting on behalf of the field team

As per the following wiki

processors.wiki.ti.com/.../BIOS

On AM572x TI-RTOS has SMP support for  thread scheduling.

Follow up questions 

  • Are peripheral libraries are SMP aware? I’m focused only on A15 cores.
  • File system? TCP/IP stack?
  • Is it transparent for application or need local treatment per application use-case?

 

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 95265 points
    Hi,

    SMP mode will not be applicable for AM571x as it will require more than 1A15 core.

    Platform software : Drivers and NDK/NIMU are not validated with SMP configuration. Default uses AMP. Overall drivers if run from a task pinned down to a specific core it should work.

    Regards, Eric
  • 0 in reply to lding
    TI__Guru** 116560 points

    Mukul/Carlo,

    Here is the public documentation slides that summaries the SMP mode feature in SYSBIOS. It indicates that all SYSBIOS thread types and features have been tested in SMP mode with certain runtime modules providing a special SMP aware version.
    processors.wiki.ti.com/.../Public_SmpBiosSlides.pdf

    The performance and benchmarks on Slide 13 to Slide 16 shows SMP and non-SMP features tested on DRA7x/J6 (on A15 and M4) and on K2H(A15) when the feature was enabled in the BIOS kernel.In general, you will see SMP numbers are higher because there is a greater overhead involved. Kernel APIs need to acquire an inter-core lock versus simply disabling interrupts before executing critical sections. As Eric indicated the LLD drivers by default get tested in AMP mode only so there may be additional sanity testing to ensure it doesn`t affect functionality.

    A good way to port existing single core AMP mode application to SMP mode is provided in slide 17 which I am summarizing here:

    Step 1: Enabled SMP mode :

    BIOS.smpEnabled = true;

    Note: Change runtime modules to inlcude SMP aware version.

    Step 2: For initial sanity testing, force all tasks to run on core 0:

    Task.defaultAffinity = 0; 

    Step 3: Once basic functionality of the merged applications has been demonstrated,

    either remove Task.defaultAffinity setting or replace it with for non real time/background tasks using  

    Task.defaultAffinity = Task.AFFINITY_NONE;

    Note: Provide default affinity = 0 for critical tasks that require real time performance.

    Let us know if you have any further questions with your evaluation.

    Regards,
    Rahul

  • 0 in reply to lding
    TI__Guru* 84435 points
    Carlo
    >>SMP mode will not be applicable for AM571x as it will require more than 1A15 core.

    For completeness, Rogerio wanted me to add that while your original question was focused on A15 for SMP support.
    AM572x supports SMP on A15s as we dual A15 (+2 DSP).
    AM571x/70x does not support SMP on A15 as these are single A15 (+DSP) devices
    However all AM57x family devices do have two dual Cortex M4 (IPU1 and 2) - these DO support SMP (as listed in the wiki).

    Hope this helps.
    Regards
    Mukul
  • 0 in reply to Mukul Bhatnagar
    TI__Mastermind 24350 points
    Hi Rahul /Mukul
    thank you very much
    please I need other clarification on SMP which could be useful to community members too :
    - considering the case to be on AM572x and interest is on SMP on A15 cores , my concerns are how the cores can manage queues , semaphore etc .

    so in more details :

    1. Will message queues, semaphores work correctly if post/get called on different cores? can we enable this ?
    2. Will semaphore (binary) or messages work correctly if posted from ISR in core 0 and received on core 1 ? any limitation/suggestion ?
    3. What tools are recommended for data synchronization across cores like spinlocks, memory barriers, etc.?
    4. Is cache coherent across cores or need explicit invalidation to maintain data consistency when producer and consumer run of different cpus.

    thank you very much
    regards
    Carlo
  • 0 in reply to Colombo Carlo
    TI__Guru** 116560 points
    Carlo,

    Please refer to my responses below. I have also notified the TI RTOS SMP BIOS expert for further inputs on memory barriers.

    1. Will message queues, semaphores work correctly if post/get called on different cores? can we enable this ?
    2. Will semaphore (binary) or messages work correctly if posted from ISR in core 0 and received on core 1 ? any limitation/suggestion ?
    -> Semaphore, message queues don`t have a any core affinity. You can post and pend on semaphores on any of the cores provided you have tasks and HWI with no core affinity. for more flexibility Core affinity can be set for HWI and Tasks to force execution on a given core but SWI always executes core 0


    3. What tools are recommended for data synchronization across cores like spinlocks, memory barriers, etc.?
    For data synchronization and memory barriers, please refer to the E2E discussion regarding concerns around SMP mode execution below:
    e2e.ti.com/.../432673

    As Ashish mentioned :
    On the Cortex-A15, barriers are required to guarantee correct operation and we do have them where required in the BIOS kernel. All SYS/BIOS synchronization primitives internally disable interrupts (call Hwi_disable/enable) to guarantee mutual exclusion. When running in SMP mode, in addition to disabling interrupts the primitives also acquire an inter-core lock. The inter-core lock implementation for Cortex-A15 executes the necessary barrier instructions.

    Is cache coherent across cores or need explicit invalidation to maintain data consistency when producer and consumer run of different cpus.

    -> I need to check with the TI RTOS team if the SMP mode configuration provides cache coherent environment. Currently the only guidance around this topic that I could find is the scheme for time critical tasks to take advantage of warm cache in a SMP mode environment as has been described here:
    processors.wiki.ti.com/.../BIOS

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    TI__Mastermind 21645 points

    Rahul Prabhu said:

    Is cache coherent across cores or need explicit invalidation to maintain data consistency when producer and consumer run of different cpus.

    -> I need to check with the TI RTOS team if the SMP mode configuration provides cache coherent environment. Currently the only guidance around this topic that I could find is the scheme for time critical tasks to take advantage of warm cache in a SMP mode environment as has been described here:
    processors.wiki.ti.com/.../BIOS

    Yes, the caches are kept coherent by the SCU hardware in a multi-processor A15 sub-system.

    Rahul Prabhu said:

    3. What tools are recommended for data synchronization across cores like spinlocks, memory barriers, etc.?
    For data synchronization and memory barriers, please refer to the E2E discussion regarding concerns around SMP mode execution below:
    e2e.ti.com/.../432673

    I wanted to add that the SYS/BIOS synchronization primitives like GateMutexPri, GateHwi, Semaphore, etc. can be used in a SMP environment too. For example, if you want to protect a data structure against simultaneous read-modify-write from two Tasks running on different cores, you can use a GateMutexPri to protect the data structure.

    Best,

    Ashish

  • 0 in reply to Ashish Kapania
    TI__Mastermind 24350 points

    Hi Ashish

    thank you

    please considering I ll use  RTOS , where can I find  SMP examples  for it ?  info on how to use APIs  for memories ?

    Is it possible to get code examples that show how to share information  over shared memories ?

    any suggestion/info is very welcome

    regrards

    Carlo

  • 0 in reply to Colombo Carlo
    TI__Guru** 116560 points

    Carlo,

    The only SMP mode examples for A15 core in the Processor SDK are the DRA7xx IPC examples  that are found ipc_3_47_01_00\examples\DRA7XX_bios_elf (host configuration uses SMP mode enabled) and POSIX SMP demo examples:

    The POSIX demo shows how pthreads_barrier can be used for task synchronization but doesn`t have any memory barriers as far as I know.

    In SMP mode a single copy of the kernel is running on both cores so as Ashish mentioned application developer can use gates, semaphores etc to implement barriers and synchronization between tasks. The documentation of these Gates is available at :

    Please note that Gates should only be used in Tasks and not in HWI and SWI as these thread types must run to completion without blocking.

    Regards,

    Rahul