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AM5728/TI-RTOS: Registering different ISR for different MSI interrupts

Manjula KS
Intellectual 430 points

Part Number: AM5728

Tool/software: TI-RTOS

Hi,

I have a problem that I am receiving msi1 and msi2 interrupts so close that I am missing msi2 interrupt completely. Is there any way that I can register 2 ISR for these 2 msi interrupts. 

Thanks & Regards

Manjula

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 430 points

    Like I want a solution similar to what we have in linux

    In linux we have pci_alloc_irq_vectors() which RC uses to allocate requested no of vectors for the msi vectors and then using the request_irq (and the helper function pci_irq_vector which gets the vector no ) and the allocated vector number I can register multiple ISR one for each msi vector.

    Some similar thing is possible in AM5728 RTOS also? I need to register 2 ISR one for msi1 and one for msi2 so that the 2 interrupts are serviced independently without timing concern.

  • 0 in reply to Manjula KS
    TI__Guru* 95265 points
    Hi,

    When you compare to Linux, do you mean the TI Processor SDK Linux running on AM57x device?

    Regards, Eric
  • 0 in reply to lding
    Intellectual 430 points
    I am omparing to regular linux implementation not ti linux sdk
  • 0 in reply to Manjula KS
    TI__Guru* 95265 points
    Hi,

    From AM572x TRM, section 24.9.4.6 PCIe Controller Interrupt Requests, there are two interrupt lines, main and MSI HW interrupt line. Only MSI HW interrupt line can be used for MSI interrupt, in our code we have one ISR registered for this interrupt and reads the MSI control interrupt bits to determine which vector came in. I am not sure if we can register multiple ISR each for a vector. But if you only have two MSI vectors you know which bits will be set, you can try to optimize the ISR code just processing those two vectors?

    Regards, Eric
  • 0 in reply to lding
    Intellectual 430 points

    When i receive msi1 and msi2 at some delay I am able to receive both the interrupts. If msi1 and msi2 overlap/close then onwards I am missing any msi1/msi2 interrupts. Not receiving interrupts at all.

    Thanks & Regards

    Manjula

  • 0 in reply to Manjula KS
    Intellectual 430 points

    Actually I have 4 msi interrupts. The scenario is I will receive interrupts any time. It may overlap and it may not. So I need to have 4 ISR for each MSI interrupts. Is there any possibility I can implement with 4 ISRS.

    Please reply.

    Thanks & Regards

    Manjula

  • 0 in reply to Manjula KS
    Intellectual 430 points

    Hi,

    Any hints on this please.

  • 0 in reply to Manjula KS
    TI__Guru* 95265 points
    Hi,

    You can only register one interrupt for the MSI, not one interrupt for each MSI vector (here you used 4 vectors). To speed up the ISR processing:

    do {
    ipr_orig = read pciePlconfMsiCtrlIntStatusReg (which may have up to 4 bits set in your case)
    for (ipr = ipr_orig, i = 0; ipr; ipr>>=1, i++)
    {
    if (ipr & 1)
    {
    ISR code
    }
    }
    } while (ipr_orig);

    Try to see if it helps!

    Regards, Eric
  • 0 in reply to lding
    Intellectual 430 points

    Actually i am doing dma receive from fpga to rc in my isr function as a swi function. I.e., when i receive msi1 interrupt i am calling swi_post and doing dma transfer  inside that. I am receing interrupts at 5us delay continously. Dma trnsfer is getting delayed so i am missing interrupts.

    Please give me solution i have do dma transfer as part of hardware isr and still receive all interrupts and data correctly

  • 0 in reply to Manjula KS
    TI__Guru* 95265 points
    Hi,

    So you have MSI interrupt at 5 us interval, with different MSI vectors? And inside ISR you do an EDMA transfer, how long does it take for the ISR code to do this? Can it be finished within 5us? Probably not, I think the best way is reduce the MSI interrupt frequency, and using EDMA to transfer a bigger block of data inside ISR?

    Regards, Eric
  • 0 in reply to lding
    Intellectual 430 points
    I am integrating pcie code with arm ipc and remoteproc. I am missing msi interrupts. I am using msi address in rc as 0xfef0f00c. Can u give any hint what is causing msi interrupt misses. ISR is getting called but pendingbits.msi is not set.
  • 0 in reply to Manjula KS
    TI__Guru* 95265 points
    Hi,

    "ISR is getting called but pendingbits.msi is not set." ====> can you clarify this is a new issue or not? In the past, you had ISR missing at fast PCIE MSI rate. Was that resolved? Now the issue is that you have MSI ISR received every time but pendingbits.msi is not set? Are you using legacy INTA/B/C/D? When you entered ISR, which pending bit is set?

    Regards, Eric
  • 0 in reply to lding
    Intellectual 430 points

    Its a new issue happening when we try to dsp pcie code with arm to boot using remoteproc. Remoteproc related entries are made in cfg file and resource table is updated for pcie. Any hints why pendingbits.msi is not set? Fpga is sending msi interrupts. There is no legacy interrupts. If dsp pcie code is run alone without arm and remote proc i am not having any issues.

  • 0 in reply to Manjula KS
    Intellectual 430 points

    The pcie addresses are mapped in resource_table.h. 8MB size starting from 0x51000000 for config space and 256MB size starting from 0x20000000. when msi interrupt happens the addresses 0x51002034 which is pending bits.msi and 0x51000830 is msibits[0].msiCtrlIntStatus should be set. but these bits are not set when the pcie code is run with remoteproc.

    Meaning the address that gets set at runtime is not reflected properly. Any issue with remoteproc integration please help.

    Thanks & Regards

    Manjula

  • 0 in reply to Manjula KS
    TI__Guru* 95265 points
    Can you clarify what operating system A15 runs? Linux? TI-RTOS? Where the PCIE ISR code runs? DSP? M4? If the ISR is entered, the register bits must have been set, but may be mapped to a different location from remoteproc? I am not familiar with remoteproc, maybe you can open a new thread with clear description so I can ask people from IPC/remoteproc for help.

    Regards, Eric
  • 0 in reply to lding
    Intellectual 430 points

    The issue is resolved. In the Linux dts file running in ARM15 we disabled the entries for pcie. With this the DSP pcie alone is running and this solved the issue