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AM5K2E02: SerDes interface

Part Number: AM5K2E02

From customer:

I’m working on a project using the AM5K2E02 processor.

 

I’m currently looking at the SerDes interface for a few peripherals. I have a couple of questions regarding the example code given in the SDK:

  1. The example code inserts values into a large number of registers which the guide (SPRUHO3A) marks as reserved. Some of these values differ depending on the peripheral being configured. For the purpose of certification/qualification, are you able to provide a breakdown of these reserved registers and their purpose?

  2. In the example for SerDes configuration of the PCIe peripheral, the code sets configures the peripheral as a 4-lane PHY-A; whereas the guide (SPRUHO3A) describes the PCIe peripheral as using a 2-line PHY-A. Are the Lane 2/3 register values necessary, or can they be ignored?

    The SDK file I have been looking at is located at: pdk_k2e_4_0_9/packages/ti/csl/src/ip/serdes_sb/V0/csl_wiz8_sb_refclk100MHz_pci_5Gbps.c