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66AK2H14: DDR3A and DDR3B

alireza noormouhamamdi
Prodigy 220 points

Part Number: 66AK2H14
Other Parts Discussed in Thread: TCI6638K2K, TCI6636K2H

Hello everyone.

Recently I have succeeded that program MPAX registers, and load my DSP codes from CCS into DSPs, when LINUX was working in the  DDR3A ( with defining a custom platform and set a new linker command, I dedicated 512M  for ARMs and 1536M dor DSPs) and everything was OK. I know that if I want to load my code to DSPs from LINUX, I must use mpmcl to do that and also know that the mem_reserve variable in the Uboot is to set Dedicated memory to DSPs (and I did all of these).

Now, we know there is another memory in the EVMK2H, that call it DDR3B, and it is an onboard memory. My question is that, is it possible to load my codes to DSPs from filesystem in LINUX  to this memory?

Actually, I want to run LINUX in DDR3A and my massive codes in DSPs with DDR3B, simultaneously.

Is it possible and if yes, how?  

  • 0
    TI__Guru**** 161600 points
    Hi,

    Yes, DDR3B is recommended to be enabled & used from DSP side. See:
    e2e.ti.com/.../2042410

    It is accessible from 00 6000 0000, but the memory space is limited to 512MB. Depending on your DDR3A_REMAP_EN configuration you can access the whole 2GB of your ddr3b memory from 00 8000 0000.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Prodigy 220 points

    Hi Yordan.

    I changed DDR3A_REMAP_EN  before in BMC command, but after that, even Uboot didn't raise! ( Maybe there are some points that I don't know)

    As we can see in the datasheet, the address between 00 8000 0000 to 00 FFFF FFFF in DSP view are DDR3B, so why I can't access it? (when I load my codes to DSPs through CCS, LINUX crash. this is so clear that CCS is loading data to LINUX kernel's address but based on the datasheet, DDR3A that LINUX will load on it, has an address between 08 0000 0000 to 09 FFFF FFFF)

    once again  I emphasize that I want to have 2G DDR3A for LINUX and 2G DDR3B for DSPs that load my program to DSPs through mpmcl.

  • 0 in reply to alireza noormouhamamdi
    TI__Guru 50170 points

    Hi, Alizera,

    There was a discussion on E2E forum regarding the access of 0x8000 0000 from DSP in e2e.ti.com/.../1752013 which you may want to take a look to see if it applies to you.

    The access to DDR3B from LInux has been disabled and not supported in Processor SDK as indicated in the e2e link provided in Yordan's earlier reply.

    Hope these info helps.

    Rex

  • 0 in reply to Rex Chang
    Prodigy 220 points

    Hi Rex and thank you

    So, as I reviewed the link that you mentioned, we only use 512MB of DDR3B via mpmcl and its address is  00 8000 0000 to 00 9FFF FFFF . 

    Is it True?

    If yes, if iI want to change my DDR3A from 2GB to 4GB ( I mean to change its hardware), which file need to be set in SDK or anywhere?

  • 0 in reply to alireza noormouhamamdi
    Prodigy 220 points

    Hi
    I defined a custom platform for using of 512MB of DDR3B in DSPs. I also set MPAX register, but I got this error in CCS

    C66xx_0: File Loader: Verification failed: Values at address 0x60000000 do not match Please verify target memory and memory map.
    C66xx_0: GEL: File: C:\Users\User\workspace_v7\hello_TCI6638K2K_C66XX\Debug\hello_TCI6638K2K_C66XX.out: a data verification error occurred, file load failed.
    what is the problem?

  • 0 in reply to alireza noormouhamamdi
    TI__Guru 50170 points
    Hi, Alireza,

    Are you using a TCI6638K2K or TCI6636K2H? What Processor SDK release are you based on?

    Rex
  • 0 in reply to Rex Chang
    Prodigy 220 points

    Hi Rex.
    I think it is TCI6638K2K and I attach its photo.
    Processor SDK release is 0.4.03.00.05
    I cant access 512MB of DDR3B until now with mpmcl and CCS.
    How can I do that?

  • 0 in reply to alireza noormouhamamdi
    TI__Guru**** 161600 points

    Hi,

    Regarding accessing ddr3b with CCS project did you set your cmd file with DDR3B region staring from 0x60000000?

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    Prodigy 220 points

    Hi Yordan.

    Yes, I did. As I understood until now, platform and cmd file have the same concept and they will complete the final linker cmd. I attached my platform in the previous comment. and this is my cmd file  contents

    SECTIONS
    {
    .text > DDR3B_DSP_SHARED
    .stack > L2SRAM
    .bss > DDR3B_Private_Core
    .cinit > L2SRAM
    .cio > L2SRAM
    .const > DDR3B_DSP_SHARED
    .data > DDR3B_Private_Core
    .neardata > DDR3B_Private_Core
    .rodata > L2SRAM
    .switch > DDR3B_DSP_SHARED
    .sysmem > DDR3B_DSP_SHARED
    .far > DDR3B_Private_Core
    .fardata > DDR3B_Private_Core
    .testMem > L2SRAM
    .farData > DDR3B_Private_Core
    }

    but it didnt work. Although I did the same setup for DDR3A and it worked.