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Linux/AM5728: IPU cannot read CMEM memory

Part Number: AM5728


Tool/software: Linux

Hi,

I have a problem with CMEM on AM5728.

Interface among ARM, DSP and IPU(M4) Core is available via CMEM shared memory.

But there is a problem that the IPU cannot read the CMEM memory area.

The part written by IPU is read well by ARM or DSP.

However the part written by ARM or DSP is not read by IPU.

R/W works well between ARM and DSP.

The settings are as follows.

SDK Version : ti-processor-sdk-linux-rt-am57xx-evm-03.01.00.06

 1. Kernel device tree (am572x-idk.dts)

           reserved-memory {

                     #address-cells = <2>;

                     #size-cells = <2>;

                     ranges;

                     ipu1_cma_pool: ipu1_cma@95800000 {

                                compatible = "shared-dma-pool";

                                reg = <0x0 0x95800000 0x0 0x2000000>; //32M

                                reusable;

                                status = "okay";

                     };

                     ipu2_cma_pool: ipu2_cma@97800000 {

                                compatible = "shared-dma-pool";

                                reg = <0x0 0x97800000 0x0 0x2000000>; //32M

                                reusable;

                                status = "okay";

                     };

                     dsp1_cma_pool: dsp1_cma@99800000 {

                                compatible = "shared-dma-pool";

                                reg = <0x0 0x99800000 0x0 0x2000000>; //32M

                                reusable;

                                status = "okay";

                     };

                     dsp2_cma_pool: dsp2_cma@9b800000 {

                                compatible = "shared-dma-pool";

                                reg = <0x0 0x9b800000 0x0 0x2000000>; // 32M

                                reusable;

                                status = "okay";

                     };

                     cmem_block_mem_0: cmem_block_mem@a0000000 {

                                reg = <0x0 0xa0000000 0x0 0x0c000000>;

                                no-map;

                                status = "okay";

                     };

       cmem_block_mem_1_ocmc3: cmem_block_mem@40500000 {

           reg = <0x0 0x40500000 0x0 0x100000>;

           no-map;

           status = "okay";

       };

           };

 

           cmem {

                     compatible = "ti,cmem";

                     #address-cells = <1>;

                     #size-cells = <0>;

                     #pool-size-cells = <2>;

                     status = "okay";

                     cmem_block_0: cmem_block@0 {

                                reg = <0>;

                                memory-region = <&cmem_block_mem_0>;

                                cmem-buf-pools = <1 0x0 0x0c000000>;

                     };

                     cmem_block_1: cmem_block@1 {

                                reg = <1>;

                                memory-region = <&cmem_block_mem_1_ocmc3>;

                     };

           };

 

2. IPU(M4) modify - rsc_table_vayu_ipu.h 


#define IPU_CMEM_IOBUFS 0x85000000  //=> virtual address of the DSP memory section

#define CMEM_PHYS_IOBUFS 0xA0000000 //=> physical address of the CMEM (shared) memory section

#define IPU_CMEM_IOBUFS_SIZE (SZ_1M * 192) //=> size of the CMEM section

struct my_resource_table ti_ipc_remoteproc_ResourceTable = {

{

        TYPE_DEVMEM,

        IPU_CMEM_IOBUFS, CMEM_PHYS_IOBUFS,

        IPU_CMEM_IOBUFS_SIZE, 0, 0, "IPU_CMEM_IOBUFS",

},

};


3.  cmem

 

  • Hi,

    Which Linux SDK is this?

    Best Regards,
    Yordan
  • ti-processor-sdk-linux-rt-am57xx-evm-03.01.00.06
  • Hi, Henry,

    Please double-check your caching properties for the said region. You may have to invoke a Cache_invalidate() if the region is cacheable.

    Rex
  • Hi Rex,

    cache is used as noncache.

    Is there anything else I need to check?

    Best Regards,

  • Hi Henry,

    Please share your IPU cfg and config.bld/linker cmd file as well.

    Can you try doing a cache write back after writing and a cache invalidate before reading?

    Can you elaborate more on the issue you're seeing? Is the IPU reading incorrect data?
  • Hi Sahin,

    Thank you for your reply.

    Please refer to as below.

    1. config.bld

    var evmDRA7XX_ExtMemMapIpu1 = {

        EXT_CODE: {

            name: "EXT_CODE",

            base: 0x00004000,

            len:  0x000FC000,

            space: "code",

            access: "RWX"

        },

        EXT_DATA: {

            name: "EXT_DATA",

            base: 0x80000000,

            len:  0x00200000,

            space: "data",

            access: "RW"

        },

        EXT_HEAP: {

            name: "EXT_HEAP",

            base: 0x80200000,

            len:  0x00300000,

            space: "data",

            access: "RW"

        },

        TRACE_BUF: {

            name: "TRACE_BUF",

            base: 0x9F000000,

            len:  0x00060000,

            space: "data",

            access: "RW"

        },

        EXC_DATA: {

            name: "EXC_DATA",

            base: 0x9F060000,

            len:  0x00010000,

            space: "data",

            access: "RW"

        },

        PM_DATA: {

            name: "PM_DATA",

            base: 0x9F070000,

            len:  0x00020000,

            space: "data",

            access: "RWX"  /* should this have execute perm? */

        }

    };

    2. config file

    0020.Ipu1.cfg

    8540.IpuAmmu.cfg

    On the IPU, it is read as 0x0 only. ARM or DSP read correctly data.

    Best Regards,

  • Hi Henry,

    The configuration looks OK. Did you try doing a cache write back and invalidate? This could help us narrow down whether it's a cache issue.
  • Hi Sahin,

    Sorry but I don’t understand invalidation though I don’t use any cache.

    Thanks.

  • Hi Sahin,

    Do you think there will be possibility to be worked as cached although they set it as non-cached already?
    Or Is there any other configuration should be set to make CMEM to be non-cached in addition to above 'alloc_params.flags = CMEM_NONCACHED'?

    It seemed there was no issue with 'alloc_params.flags = CMEM_CACHED' and I requested to check this again.

    In the meantime, could you please let me know what should be done to make CMEM to be 'NONCACHED'?


    Thanks and Best Regards,
    SI.

  • Hi Sung-IL,

    I'm sorry this was missed. Were you able to resolve the issue?

  • Hi,

    Unfortunately I can not remember how it was gone.
    I requested several tests on latest SDK, but have not got any response after that.
    I assumed this issue was resolved as their product development using AM57x is goes well, and I'm afraid it is too late to check this issue again.
    Thanks for checking this issue again.

    Thanks and Best Regards,
    SI.