AM3352: DMTimer2 behavior

Mukul Bhatnagar

Part Number: AM3352

Posting on behalf of a customer

AM3352 has 6 DM timers (TIMER2-TIMER7). We noticed that TIMER2 is running at about 32KHz, and it's registers are accessible even before the first code instruction is executed (i.e. none of the registers is configured by our application). Why? Could you help us to understand this?

TIMER3-TIMER7 registers are not accessible. There is nothing in the documentation that suggests that TIMER2 is different somehow.

Regards

Mukul

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

My guess would be that DMTimer2 is initialized by the ROM code, however I don't have access to this, so cannot confirm. I have notified the factory team. They will respond here.

0 Steve Kipisz over 7 years ago in reply to Biser Gatchev-XID

TI__Genius 15510 points

The boot ROM uses DMTIMER2 for timeouts. You can use it in your code since the boot ROM is done when your code runs. Actually, u-boot uses DMTIMER2 for timeouts. Once u-boot is done and your code runs, you can use it.

Steve K.

0 Mukul Bhatnagar over 7 years ago in reply to Steve Kipisz

TI__Guru* 83855 points

Thanks for clarifying this Steve. That explains why DMTIMER2 does not need any additional initialization while other DMTIMERs do.

0 VC Kumar over 7 years ago in reply to Mukul Bhatnagar

TI__Intellectual 1260 points

Mukul, Steve

Should our documentation be updated to reflect this?

Thanks

0 VC Kumar over 7 years ago in reply to VC Kumar

TI__Intellectual 1260 points

A related question from the customer:

There seems to be a discrepancy. The TRM indicates that internal 32KHz clock is the default source but the register indicates otherwise.
Our code does not write the register, so is it something that the ROM bootloader does?

0 Steve Kipisz over 7 years ago in reply to VC Kumar

TI__Genius 15510 points

Actually, the TRM shows the default is CLK_M_OSC but I connected with JTAG and saw the default clock source is the 32KHz clock. The value I read from CLKSEL_TIMER2_CLK is 2. I'll submit a ticked to get this fixed in the next TRM.

Steve K.

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AM3352: DMTimer2 behavior