Other Parts Discussed in Thread: TIDEP-0088
Hi,
I am presently working on interfacing Circular Microphone Board ( CMB ) with AM572x processor, I am using McASP7 channel of Sitara AM572x.
In my case CMB is the master and hence McASP7 acts as the slave, CMB is giving Frame Sync, Bit Clock and data signals to the McASP7 receiver. Once I configure the McASP7 and observe the "MCASP_RXSTAT" I am getting to see that "RCKFAIL" bit is being set. Hence, I found for the below attached document and found the following steps.
a. Configure receive clock failure detect logic (RMIN, RMAX, RPS) in the receive clock check control
register (RCLKCHK).
b. Clear receive clock failure flag (RCKFAIL) in the receive status register (RSTAT).
c. Wait until first measurement is taken (> 32 AHCLKR clock periods).
d. Verify no clock failure is detected.
e. Repeat steps b–d until clock is running and is no longer issuing clock failure errors.
f. After the receive clock is measured and falls within the acceptable range, the following may be
enabled:
i. receive clock failure interrupt enable bit (RCKFAIL) in the receiver interrupt control register
(RINTCTL)
ii. mute option (RCKFAIL) in the mute control register (AMUTE)
How to achieve to wait until first measurement is taken (> 32 AHCLKR clock periods)?
I also went through the below post, but I am clueless.
Also, can anyone please send me the exact configuration steps and the registers which I am supposed to write on to receive the data from the CMB.
I used K2G interface code with CMB as reference but still I am unable to read audio data.
Also, what is the maximum data rate which McASP receive can support.
I am first time working on Audio, please guide me on me issues.
Thanks and Regards,
Janardan M
