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Linux/AM5728: Frequency configuration for DSP core

Jimit Patel
Intellectual 570 points
Part Number: AM5728

Tool/software: Linux

I am using AM5728 on a custom board. The DSP core is running TI-RTOS and the A15 is running Linux. I need to run the DSP core at OPP_OD (700MHz) all time. Is there any way I can set frequency of the DSP core from Linux? I searched through the forums and came across the solution involving modifying the gel file from CCS while debugging. But I am looking for means to do so from Linux. Ideally, I would like to have means of setting the new frequency as default for the DSP core so it always operates at the new frequency (across power cycles).

-Jimit

  • 0
    TI__Mastermind 30536 points
    Jimit,

    I want to make sure that you've looked into how running at OD may impact POH and that meets the needs for your product.

    We'll look further into the best way to do what you've asked and get back to you soon.
  • 0 in reply to RonB
    TI__Guru 50170 points
    Hi, Jimit,

    The DSP frequency is configured in u-boot. please takes a look at u-boot/arch/arm/mach-omap2/omap5/fdt.c in which DSP clock is programmed in ft_opp_clock_fixups() per dra7_opp_dsp_clk_rates[]. I would suggest to change the dsp frequency in Kernel dra7-clock.dtsi as well to match up with what is configured in u-boot.

    /* DSPEVE voltage domain */
    u32 dra7_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = {
    {}, /*OPP_LOW */
    {600000000, 600000000, 400000000}, /* OPP_NOM */
    {700000000, 700000000, 466666667}, /* OPP_OD */
    {750000000, 750000000, 500000000}, /* OPP_HIGH */
    };


    static void ft_opp_clock_fixups(void *fdt, bd_t *bd)
    {
    const char **clk_names;
    u32 *clk_rates;
    int ret;

    if (!is_dra72x() && !is_dra7xx())
    return;

    /* fixup DSP clocks */
    clk_names = dra7_opp_dsp_clk_names;
    clk_rates = dra7_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)];
    ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM);
    if (ret) {
    printf("ft_fixup_clocks failed for DSP voltage domain: %s\n",
    fdt_strerror(ret));
    return;
    }

    Rex