• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 99 subscribers
  • Views 1281 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

pdk_am335x_1_0_2: UART DMA driver is not available

RTOS/AM5728: UART DMA issues

Yves Bonin
Prodigy 100 points
Part Number: AM5728
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

I am developing UART interfaces into the IPU1 of the AM5728 for ports 1 and 8.

I have successfully enabled DMA mode for UART1 and data transfer is perfect.

EDMA-TCC is OK as both TX and RX ISR handlers are called (UART_txIsrHandler and UART_rxIsrHandler) so that my callbacks are also called.

So, I tried the same thing with UART8, but I found that EDMA channels were not good by default within the UART LLD, so I change them according to spec document (DMA_CROSSBAR_146 and 147).

The config is all good as the UART8 opens in a good way.

I am also seeing data transfered on the TX pin.......but my EDMA-TCC doesn't work as UART_txIsrHandler is never called.....thus, my callback neither....

Is there something I missed for UART8, compared to UART1 ????

I also want to mention that UART8 works perfectly without DMA mode enabled.....so no hardware issues, nor config issues here....

Thanks.

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 95265 points
    Hi,

    In the uart\soc\am572x\uart_soc.c, please check the structure uartInitCfg[], the [0] is for UART 1, .... [7] is for UART8

    Do you use below for UART8:
    CSL_UART_7_MODULE_FREQ,
    CSL_EDMA3_CHA_UART7_RX,
    CSL_EDMA3_CHA_UART7_TX,

    And the CSL define:
    #define CSL_EDMA3_CHA_UART7_RX 51
    /* UART7 Transmit Event */
    #define CSL_EDMA3_CHA_UART7_TX 50

    This overlaps
    #define CSL_EDMA3_CHA_UART1_RX 51
    /* UART1 Transmit Event */
    #define CSL_EDMA3_CHA_UART1_TX 50

    Do you use UART1 and UART8 at the same time?

    From AM572x TRM
    Table 16-6. Connection of The Device DREQs to The DMA_CROSSBAR Inputs
    DMA_CROSSBAR_49 UART1_DREQ_TX UART module 1 - transmit request
    DMA_CROSSBAR_50 UART1_DREQ_RX UART module 1 - receive request

    It seems the TRM is off CSL code by "1".

    So, as in the TRM
    DMA_CROSSBAR_146 UART8_DREQ_TX UART module 8 - transmit request
    DMA_CROSSBAR_147 UART8_DREQ_RX UART module 8 - receive request

    The CSL you need define UART7_TX as 147 and UART_RX as 148? Will this help?

    Regards, Eric
  • 0 in reply to lding
    Prodigy 100 points

    Hi,

    Yes, I am using both UART1 and UART8 simultaneously.

    For UART8, before you answer, I tried using DMA_CROSSBAR_146/147 (real values were 145/146 as I thought I had to do -1, not +1, like on UART1).

    It didn't work for me.

    Now, following your answer above, I tried DMA numbers 148/149 as your suggestion, but same results..... UART_open() fails....

    So, I tried the value EDMA3_DRV_DMA_CHANNEL_ANY and UART_open() now works.

    Indeed, the UART LLD gave me back the DMA events 0 and 4 as unused DMA crossbar numbers to use.

    But, at the end, I am having the same results.... I am seeing the traffic on UART8_TX pin, but the EDMA3 TCC never calls my registered callback.

    Note that my callback is called successfully when DMA is disabled.

    Again, I am telling you that EDMA works for UART8, but I am not getting the EDMA_TCC !!!!!

    Is this an IRQ issue ???  or a DMA issue ???

    Some more details for you on my config:

    • IPU1 uses EDMA3 instance 0
    • UART1 uses CSL_XBAR_INST_IPU1_IRQ_24 on crossbar IRQ_CROSSBAR_67
    • UART8 uses CSL_XBAR_INST_IPU1_IRQ_25 on crossbar IRQ_CROSSBAR_219
    • UART1 uses DMA_CROSSBAR_49 for RX and DMA_CROSSBAR_50 for TX
    • UART8 uses EDMA3_DRV_DMA_CHANNEL_ANY for both RX and TX (I am getting back unused DMA events 0 and 4 from UART LLD)
      • I tried to use DMA_CROSSBAR_146/147/148/150 but no luck with UART_open()
    We really need some help on this bug please.
    So, keep us in touch with your findings and/or new things you want us to try.
    Do you have any customer or an in-house test that uses any UART from 6 to 10 in DMA mode in the IPU ?
    Thanks.
  • 0 in reply to Yves Bonin
    Prodigy 100 points
    Hi,

    Ok now I have the UART8 TX side working by fixing my DMA crossbars.....
    But, I am getting an IPU crash when receiving traffic onto the UART8 RX side.
    Here is the crash:

    [0][ 10.368] [t=0x00000001:0716e7da] ti.sysbios.family.arm.m3.Hwi: ERROR: line 1104: E_hardFault: FORCED
    [0][ 10.368] ti.sysbios.family.arm.m3.Hwi: line 1104: E_hardFault: FORCED
    [0][ 10.368] [t=0x00000001:071b8537] ti.sysbios.family.arm.m3.Hwi: ERROR: line 1181: E_busFault: IMPRECISERR: Delayed Bus Fault, exact addr unknown, address: e000ed38
    [0][ 10.368] ti.sysbios.family.arm.m3.Hwi: line 1181: E_busFault: IMPRECISERR: Delayed Bus Fault, exact addr unknown, address: e000ed38
    [0][ 10.368] Exception occurred in ISR thread at PC = 0x0000d6b4.
    [0][ 10.368] Core 0: Exception occurred in ThreadType_Hwi.
    [0][ 10.368] Hwi name: {unknown-instance-name}, handle: 0x8000e4e8.
    [0][ 10.368] Hwi stack base: 0x8012dd48.
    [0][ 10.368] Hwi stack size: 0x8000.
    [0][ 10.368] R0 = 0x58820200 R8 = 0x8012d1d8
    [0][ 10.368] R1 = 0x58820200 R9 = 0x00000100
    [0][ 10.368] R2 = 0x00000003 R10 = 0x8013a738
    [0][ 10.368] R3 = 0x00000000 R11 = 0x00000003
    [0][ 10.368] R4 = 0x8013a738 R12 = 0x8012dcb0
    [0][ 10.368] R5 = 0x8012d1d8 SP(R13) = 0x80135cb8
    [0][ 10.368] R6 = 0x8012d1d8 LR(R14) = 0x0001d2ed
    [0][ 10.368] R7 = 0x00000008 PC(R15) = 0x0000d6b4
    [0][ 10.368] PSR = 0x81000019
    [0][ 10.368] ICSR = 0x00419003
    [0][ 10.368] MMFSR = 0x00
    [0][ 10.368] BFSR = 0x04
    [0][ 10.368] UFSR = 0x0000
    [0][ 10.368] HFSR = 0x40000000
    [0][ 10.368] DFSR = 0x00000000
    [0][ 10.368] MMAR = 0xe000ed34
    [0][ 10.368] BFAR = 0xe000ed38
    [0][ 10.368] AFSR = 0x00000000
    [0][ 10.368] Terminating execution...

    Is there something here that can be useful to debug my problem ?

    Thanks.
  • 0 in reply to lding
    Prodigy 100 points
    Reducing both RX and TX thresholds seem to have helped.
    So, at the end, we think that we have some performance issues within the TI UART LLD when using 2 UARTS in EDMA mode at 3Mbps and up.
    Is that expected ?
    Moreover, is it true to think that we can run any UART in EDMA mode at 12Mbps onto the IPU1 ?
    Thanks.
  • 0 in reply to Yves Bonin
    Prodigy 180 points
    Eric,

    We fixed the issue. When requesting the RX DMA channel in the uart_v1 driver, it uses a local variable called tcc to store the returned TCC but this value is not stored in the hwAttrs structure (hwAttrs->edmaRxTCC). In the read function, the TCC that is set in the PaRAM structure is the one from the hwAttrs structure. It was working for us with UART1 since the value in the structure was 0 and the request channel function was also returning 0 but it was not working for UART8. We patched the uart_v1 driver so it is now properly configuring the TCC in the DMA registers.

    Regards,