RTOS/PROCESSOR-SDK-AM437X: GPMC access

user5371084

Part Number: PROCESSOR-SDK-AM437X
Other Parts Discussed in Thread: AM4376

Tool/software: TI-RTOS

I want to access the first address 0x1000000(physical address) on a SRAM chip(8bits/512KByte), CPU is the AM4376, and no OS(pdk_am437x_1_0_10).

If I disable all the MMU and cache, It can work(I can get the active chip select signal from the oscilloscope). but because of other requirements, I have to enable the MMU and cache, the code is:

MMUConfigAndEnable();
CACHEEnable(CACHE_IDCACHE, CACHE_INNER_OUTER);

this functions is in the file:C:\ti\pdk_am437x_1_0_10\packages\ti\starterware\examples\example_utils\example_utils_mmu.c

but the program was throwed into AbortHandler interrupt.

How to change code to access to the first address 0x1000000(physical address)?

also, I notice that in function MMUConfigAndEnable(), there are this structure:

mmuMemRegionConfig_t regionOcmc =
            {
                0,
                NUM_SECTIONS_OCMC, /* Number of pages */
                1U*MEM_SIZE_MB, /* Page size - Min 1MB */
                MMU_MEM_ATTR_NORMAL_NON_SHAREABLE,
                MMU_CACHE_POLICY_WT_NOWA, /* Inner */
                MMU_CACHE_POLICY_WB_WA, /* Outer */
                MMU_ACCESS_CTRL_PRV_RW_USR_RW,
                FALSE /* Non Secure memory */
            };

Please explain its function.

over 6 years ago

0 Biser Gatchev-XID over 6 years ago

TI__Guru**** 393215 points

The RTOS team have been notified. They will respond here.

0 lding over 6 years ago in reply to Biser Gatchev-XID

TI__Guru* 95265 points

Hi,

You are using MMU and cache in a non-OS environment based on the Starterware code.

I looked at MMUConfigAndEnable(), it has the MMU enabled for the 4 below regions: DDR, OCMC, DEV and QSPI

/* Map the defined regions */
MMUMemRegionMap(&regionDdr, (uint32_t*)pageTable);
MMUMemRegionMap(&regionOcmc, (uint32_t*)pageTable);
MMUMemRegionMap(&regionDev, (uint32_t*)pageTable);
MMUMemRegionMap(&regionQspi, (uint32_t *)pageTable);

The start of each region:
/** Memory definitions for MMU Configurations. */
/* TODO: Need to get the below data from chip/board db. */
#define START_ADDR_DDR (0x80000000U)
#define START_ADDR_DEV (0x44000000U)
#define START_ADDR_L2_SRAM (0x40500000U)
#define START_ADDR_QSPI (0x30000000U)

So, those MMU doesn't include your GPMC address 0x1000000. You need add an entry inside MMUConfigAndEnable().

About the meaning of this structure:

typedef struct region {
uint32_t startAddr; /**< Start Address of the page */
uint32_t numPages; /**< Number of Pages in the region */
uint32_t pgSize; /**< Size of the Page (in bytes) */
mmuMemAttr_t memAttrib; /**< SO, Device, Normal (shareable ?) */
mmuCachePolicy_t innerCachePolicy; /**< Applicable for normal mem only */
mmuCachePolicy_t outerCachePolicy; /**< Applicable for normal mem only */
mmuAccessCtrl_t accessCtrl; /**< Access Permissions for the page */
uint32_t isMemSecure; /**< Secure or non secure (TRUE or FALSE) */
} mmuMemRegionConfig_t;

Regards, Eric

0 user5371084 over 6 years ago in reply to lding

Expert 2215 points

Hi Eric,

I am researching this codes.But I have some questions:

1. what is the functions of the innerCachePolicy and outerCachePolicy? I cannot find the information in the TRM.

2. In the C:\ti\pdk_am437x_1_0_10\packages\ti\starterware\examples\example_utils\example_utils_mmu.c file, OCMC RAM region startAddr is 0, is it meaning to map a 0x0 physical address to a 0x0 virtual address?

3. In the C:\ti\pdk_am437x_1_0_10\packages\ti\starterware\examples\example_utils\example_utils_mmu.c file,OCMC RAM region numPages is 1, Can I change it to a large enough number to cover address range of 0x1000000 to implement to access 0x1000000?

4. or, can I add a new code line to excute the function MMUMemRegionMap() to enable the 0x1000000 access?

0 lding over 6 years ago in reply to user5371084

TI__Guru* 95265 points

Hi,

For 1:
MMU_CACHE_POLICY_WB_WA, /**< Write back, Write allocate */
MMU_CACHE_POLICY_WT_NOWA, /**< Write through, No write allocate */
MMU_CACHE_POLICY_WB_NOWA, /**< Write back, No write allocate */

This is not from TI TRM. The AM437x device use the ARM A9 core, so you need to check ARM document to understand what the inner and outer cache policy and what to use for memory device.

For 2:
The starting address of OCMC is not zero. It was defined as zero then modified before the call:
regionOcmc.startAddr = CHIPDBBaseAddress(CHIPDB_MOD_ID_OCMCRAM, 0);
MMUMemRegionMap(&regionOcmc, (uint32_t*)pageTable);

For 3, the starting of OCMC is not zero, but should be something like: 0x4030_0000. So you can't use it to cover your GPMC address.

For 4, Yes, this is what you need to do.

Regards, Eric

0 user5371084 over 6 years ago in reply to lding

Expert 2215 points

Yes, I get it.

Thank you very much!

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RTOS/PROCESSOR-SDK-AM437X: GPMC access