AM5728: Maximum frequency of GPMC_CLK

Hi g.f.

The AM572x max GPMC_CLK frequency for synchronous mode is 88.6667 MHz (datasheet reads 11.3ns clock period, which converts to 88.5MHz, but its 11.278ns without the rounding).

On AM572x the internal GPMC functional clock (GPMC_FCLK) is derived from a 266MHz L3 clock. Dividing this by 2 with the GPMCFCLKDIVIDER results in 266MHz/2 = 133MHz, which is too fast for timing closure, so 266MHz/3 = 88.67MHz must be used.

To achieve this max freq, GPMC_FCLK = L3_ICLK_Div = CORE_X2_CLK (L3_ICLK_Div = div-by-1) = 266MHz, GPMCFCLKDIVIDER = 0x2 (div-by-3), GPMC_CLK = 266MHz / 3 = 88.67MHz

Its easiest to trace the clock through the clock tree tool for AM572x

Find CLOCKTREETOOL-SITARA on http://www.ti.com/tool/clocktreetool

Tracing backwards from GPMC in the clock tree tool to find its clock source...

GPMC clocked by L3MAIN1_L3_GICLK

L3MAIN1_L3_GICLK clocked by L3_ICLK

L3_ICLK clocked by L3_ICLK_Div

L3_ICLK_Div clocked by CORE_CLK (after Divider_L3_ICLK div-by-1 or div-by-2)

CORE_CLK clocked by CORE_X2_CLK

CORE_X2_CLK clocked by DPLL_CORE_CLKOUTX2_H12

DPLL_CORE_CLKOUTX2_H12 clocked by DPLL_CORE

DPLL_CORE clocked by CORE_DPLL_CLK

CORE_DPLL_CLK clocked by SYS_CLK1

SYS_CLK1 clocked by xi_osc0

AM437 has different clocking that allows GPMC_FCLK = 100MHz.

GPMC uses L3S_CLK

TRM Figure 6-14. Core PLL Structure shows L3S_CLK = CORE_CLKOUTM4 (200 MHz) / 2

TRM Table 6-22. Core PLL Typical Frequencies (MHz) shows CORE_CLKOUTM4 (from HSDIVIDER-M4) max freq = 200MHz (OPP100)

GPMC_FCLK = 100MHz max

GPMC_CLK = 100MHz when GPMCFCLKDIVIDER = 0 (div-by-1)

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There may be improvements in device side latency from AM437x to AM572x due to differences in ARM core (A9 to A15), ARM clock speeds (1000MHz to 1500MHz), DDR memory (800MT/s to 1066MT/s), caching and high-speed interconnect fabric. I don't believe this improvement has been measured yet.

Hope this helps,
Mark