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TMS320C6678: About CVDD voltage after VID has been validated

Naoki Kawada
Guru 19890 points
Part Number: TMS320C6678
Other Parts Discussed in Thread: LM10011

Hi,

My customer is using C6678 on their custom board and seeing boot failure. And that seems to depend on CVDD voltage after VID has been validated during the power cycle. They are using LM10011 with DC/DC circuit on their custom board to provide SmartReflex CVDD voltage.  They have cross-checked this issue on some boards. Please find the following matrix:

Board | VID | DC/DC output | DSP boot ok or not
--------------------------------------------------------------------
#1 | +1.052V | +1.050V | OK
#2 | +0.965V | +0.955V | NG (OK 2/10 power cycle)
#3 | +1.103V | +1.100V | OK

If you see #2, VID indicated 0.965V for CVDD and actually DC/DC circuit provided 0.938V (measured near by C6678) . This is actually lower than 0.965V because some voltage drop was seen in power distribution path between C6678 and DC/DC circuit. Please note, this does not still violate C6678 data sheet spec --- It says CVDD min value for operating condition is SRVnom × 0.95 (In this case, 0.965×0.95 = 0.917V), so even if we use 0.938V for CVDD, that should be ok in theory. But in this condition, they actually only saw 2 times boot success per 10 power cycles...

Now they tried to fix this voltage drop in power distribution path to provide more accurate value (0.965V), and then the board#2 boot failure has been disappeared.

Can you comment for this phenomenon ? Is CVDD min really SRVnom × 0.95 ?

Best Regards,
NK

  

  • 0
    TI__Mastermind 46460 points

    Naoki,

    How did you measure the voltage at the C6678?  The best way to make this measurement is by using a handheld multimeter to measure across one of the ceramic decoupling capacitors either directly under the DSP or on the far side from the power supply.  This will properly account for IR drop in both the CVDD plane and the VSS plane.

    How do you define successful boot?  What boot mode are you using?

    What DC-DC supply are they using?  Did the designer properly implement a remote sense connection?  Where is it connected?  Due to the power requirements of the C6678, differential remote sense is highly recommended.  Is differential remote sense used?

    Have you read the VID code from the processor?  The VID value is readable from the VCNTLID register at 0235_0014h and extracted from bits 21:16.  Please refer to the PSC User Guide for the full register definition and the device Data Manual for the full address map.

    Please add a few more columns and some more clarity to your table.  What do you mean by the voltage in the column labeled VID?  Please add a column to the table showing the VCNTL binary value from the VCNTLID register read.  Also add a column showing the differential voltage at the load using the method mentioned above.  Please show this measurement under 3 conditions: while the DSP is in reset, after a successful boot, after a failed boot (if the unit on the board ever fails).

    Are these initial prototypes?  If so, how many boards did you build?

    Tom

  • 0 in reply to Tom Johnson 16214
    Guru 19890 points

    Hi Tom,

    Tom Johnson 16214 said:
    How did you measure the voltage at the C6678?  The best way to make this measurement is by using a handheld multimeter to measure across one of the ceramic decoupling capacitors either directly under the DSP or on the far side from the power supply.  This will properly account for IR drop in both the CVDD plane and the VSS plane.

    I think they validated it on the ceramic decoupling capacitors near by DSP, but let me confirm.

    Tom Johnson 16214 said:
    How do you define successful boot?  What boot mode are you using?

    Not sure. I'll ask the same to the customer, but i guess the successful booting may be verified based on the booted application (software). 

    Tom Johnson 16214 said:
    What DC-DC supply are they using?  Did the designer properly implement a remote sense connection?  Where is it connected?  Due to the power requirements of the C6678, differential remote sense is highly recommended.  Is differential remote sense used?

    What did you mean by a remote sense connection ? As for the power design, I think they only followed the suggestions described in the HW design guide (2.2.1.4  LM10011 and Analog Controller Solutions)

    Tom Johnson 16214 said:
    Have you read the VID code from the processor?  The VID value is readable from the VCNTLID register at 0235_0014h and extracted from bits 21:16.  Please refer to the PSC User Guide for the full register definition and the device Data Manual for the full address map.

    Yes. As far as i know, VID code from DSP had been validated on that register and it showed the correct value. I believe it indicated 101000b = 0.956V in case of #2 (Sorry, I wrote it as 0.965V, but it may be typo... i'll confirm tomorrow)

    Tom Johnson 16214 said:
    Please add a few more columns and some more clarity to your table.  What do you mean by the voltage in the column labeled VID?  Please add a column to the table showing the VCNTL binary value from the VCNTLID register read.  Also add a column showing the differential voltage at the load using the method mentioned above.  Please show this measurement under 3 conditions: while the DSP is in reset, after a successful boot, after a failed boot (if the unit on the board ever fails).

    To be more accurate, VID indicator in the table is the voltage described in the Hardware design guide (Table 1 SmartReflex VID Value Mapping). Sorry for the confusion, but as i mentioned above, VID should be looked correct on their target board.And base on the value, DC/DC looked trying to provide the correct voltage for CVDD. But before reaching the power to C6678 CVDD pins, there was some drop, but it should be in C6678 operating condition. Their expectation was the successful booting (Here, I need to clarify what is booting), but actually they saw the boot failure if the did not fix the power distribution path to provide more accurate voltage on CVDD indicated by LM10011 with DC/DC. Is this answer to your question ? Or do you want to clarify more ?

    Tom Johnson 16214 said:
    Are these initial prototypes?  If so, how many boards did you build?

    Not sure about the number of boards, but i think they are in 1st prototype.

    Best Regards,
    NK

  • 0 in reply to Naoki Kawada
    Guru 19890 points

    Hi Tom,

    Some updates from the customer.

    1. Boot mode : SPI boot
    2. Definition for Boot success or not : Based on the booted SW (It output some logs via UART when the app booted correctly)
    3. Voltage measurement : They are surely checking CVDD voltage on decoupling capacitor (very) near by DSP
    4. They have totally 4 boards and they are seeing this problem on a board
    5. Updated matrix. VID has been now changed to VCNTL. 

    Board | VCNTL | DC/DC output | DSP boot ok or not
    --------------------------------------------------------------------
    #1 | 110111 | +1.050V | OK
    #2 | 101000 | +0.955V | NG (OK 2/10 power cycle)
    #3 | 111111 | +1.100V | OK

    Naoki Kawada said:
    Also add a column showing the differential voltage at the load using the method mentioned above. 

    We are not sure what was actually meant by this part. Could you please clarify ? To me, i thought you were saying that you wanted to the information (adding a row) in the table to show actual voltage drop caused by the power distribution path between DCCD and C6678 CVDD. Correct ?

    Best Regards,
    NK

  • 0 in reply to Naoki Kawada
    TI__Mastermind 46460 points

    Naoki,

    3. Voltage measurement : They are surely checking CVDD voltage on decoupling capacitor (very) near by DSP.

    This needs to be a differential measurement across the capacitor - not from the CVDD to a ground somewhere else on the board.  That is why I recommended using a handheld multimeter.

    5.  Updated table:

    Please add columns showing the differential voltage at the load using the method mentioned above (measured across a capacitor at the load using a handheld multimeter). Please show this measurement under 3 conditions: while the DSP is in reset, after a successful boot, after a failed boot (if the unit on the board ever fails).

    This CVDD voltage measurement at the load cannot be from the CVDD side of the capacitor to some random location on the VSS plane.  It must be taken differentially across a decoupling capacitor under the DSP or on the far side of it from the CVDD power source.

    Other questions still pending:  What DC-DC supply are they using? Did the designer properly implement a remote sense connection? Where is it connected?  Is differential remote sense used?

    Tom

  • 0 in reply to Tom Johnson 16214
    Guru 19890 points
    Hi Tom, I’ll ask the same to the customer : check if differential measurement for decoupling cap and and the info to the matrix and ask other pending items. I’m not HW guy, so let me clarify what you meant by a remote sence. Does it look like the method of the following method ? www.ti.com/.../slyt467.pdf
  • 0 in reply to Naoki Kawada
    TI__Mastermind 46460 points

    Naoki,

    Yes, remote sense for the CVDD power supply is the same topic that is addressed in your highlighted applications note SLYT467.

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 42545 points
    Hi Naoki,
    Can you also get the exact part number of the C6678 that the customer is using? C6678 can be purchased in different speed grades and the highest has different voltage values associated with the VID values. If the customer is using the 1.4GHz version of the part, they may be providing a core voltage value that is not correct.
    Regards, Bill
  • 0 in reply to Bill Taboada
    Guru 19890 points
    Hi Bill, Ok, i’ll Check with other pending items. Best regards, NK
  • 0 in reply to Naoki Kawada
    Guru 19890 points
    Hi, Bill

    As for the part number, it was TMS320C6678ACYPA (not 1.4Ghz bat 1Ghz variant). I`ll update you once i got more updates from the customer.

    Best Regards,
    NK
  • 0 in reply to Naoki Kawada
    Guru 19890 points

    Hi, Bill

    Sorry for the delayed response.

    Here is from my customer:

    Note:
    1. Differential voltage on decoupling capacitor has been actually evaluated under their test
    2. They are not using power sense in their custom board. 

    Best Regards,
    NK

  • 0 in reply to Naoki Kawada
    TI__Mastermind 46460 points

    NK,

    I need this table to also include the output from the AVS supply right at the power stage components during these tests.  Please provide a single table with all of this information.

    Tom

  • 0 in reply to Tom Johnson 16214
    Guru 19890 points

    Hi Tom,

    Ok, I`ll try to get the information you requested. 

    PS
    I got your name wrong in some previous post ... Sorry, Tom-san. 

  • 0 in reply to Naoki Kawada
    Guru 19890 points
    Hi Tom,

    I`m still waiting for my customer`s reply. Once i got any further information from them, i`ll update you.

    Best Regards,
    NK
  • 0 in reply to Naoki Kawada
    TI__Mastermind 46460 points

    Naoki,
    Is this still an open topic? I have not seen a response for over a week. If I do not see further discussion in the next week, I will close this thread.
    Tom

  • 0 in reply to Tom Johnson 16214
    Guru 19890 points
    Hello Tom,

    Thanks for your attention. Well, we are asking the customer, but still no reply.. I`ll update you once i got the further information.

    Best Regards,
    NK
  • 0 in reply to Naoki Kawada
    Guru 19890 points

    Hello Tom,

    Sorry for the delayed response. Here is the complete set. You will find the AVS supply in parentheses.

    table.xlsx

    With regard to #2,  I believe that should not happen. What is your thought on this ?

    Best Regards,

    NK

  • 0 in reply to Naoki Kawada
    TI__Mastermind 46460 points

    NK,

    I do not understand your question.  What do you mean by "With regard to #2,  I believe that should not happen"?

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 46460 points

    NK,

    The lack of remote sense is a significant problem.  It is not directly related to the failure of board 2 as it only shows 2.5% voltage drop from the power supply to the load.  However, board #1 which is currently booting has a 6% voltage drop.  Remote sense as discussed in SLYT467 is almost mandatory for this class device due to the different levels of current draw during operation.  I expect that this voltage will drop significantly more when you run an optimized DSP application.  Adding copper between the power supply and the load will help but not fully resolve the problem.

    There is an additional aspect of power supply accuracy that is not being discussed.  You are currently only measuring the DC average voltage.  We have not yet discussed the power supply dips that occur during step increases in load current.  These dips can be significant depending on the power supply design.  We have also not discussed high frequency switching noise.  All of these voltage disturbances must be accounted for within the 5% supply accuracy number.  Therefore, even though your DC accuracy appears to be within the acceptable range.  I expect that the voltage is dropping below acceptable levels even on the other 2 boards.

    I propose a test.  Since you have all 3 boards operating with 20-50mV of DC voltage drop, you can increase the nominal supply output from 1.100V to 1.130 by changing the feedback divider circuit that sets the nominal voltage.  You should slightly increase the resistance of the resistor connected between VOUT and the FB pin.  Therefore, the AVS step size does not change significantly.  Please provide results from this test.

    Tom

  • 0 in reply to Tom Johnson 16214
    Guru 19890 points
    Hello Tom,

    Thank you for your suggestion. They tested 1.130V initial voltage or CVDD and confirmed all boards worked correctly!

    Best Regards,
    NK
  • 0 in reply to Naoki Kawada
    TI__Mastermind 46460 points

    NK,

    This confirms that they have a deficient power supply solution.  The customer needs to implement a revised AVS power solution using remote sensing as previously stated.  They may also need to reduce the voltage drop between the AVS supply and the C6678 be either making them closer or adding copper or both.

    Tom

  • 0 in reply to Tom Johnson 16214
    Guru 19890 points
    Hi Tom,

    Thanks for your suggestions. We talked with the customer and they would consider using power sensing solution. I close the thread now.

    Thank you again for all your support!
    NK